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ATmega32A Datasheet - Sunrom Technologies

ATmega32A Datasheet - Sunrom Technologies

ATmega32A Datasheet - Sunrom Technologies

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<strong>ATmega32A</strong>19.2.1 AVR USART vs. AVR UART – CompatibilityThe USART is fully compatible with the AVR UART regarding:• Bit locations inside all USART Registers• Baud Rate Generation• Transmitter Operation• Transmit Buffer Functionality• Receiver OperationHowever, the receive buffering has two improvements that will affect the compatibility in somespecial cases:• A second Buffer Register has been added. The two Buffer Registers operate as a circularFIFO buffer. Therefore the UDR must only be read once for each incoming data! Moreimportant is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) arebuffered with the data in the receive buffer. Therefore the status bits must always be readbefore the UDR Register is read. Otherwise the error status will be lost since the buffer stateis lost.• The receiver Shift Register can now act as a third buffer level. This is done by allowing thereceived data to remain in the serial Shift Register (see Figure 19-1) if the Buffer Registersare full, until a new start bit is detected. The USART is therefore more resistant to DataOverRun (DOR) error conditions.The following control bits have changed name, but have same functionality and register location:• CHR9 is changed to UCSZ2• OR is changed to DOR19.3 Clock GenerationThe clock generation logic generates the base clock for the Transmitter and Receiver. TheUSART supports four modes of clock operation: Normal Asynchronous, Double Speed Asynchronous,Master Synchronous and Slave Synchronous mode. The UMSEL bit in USARTControl and Status Register C (UCSRC) selects between asynchronous and synchronous operation.Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRARegister. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCKpin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slavemode). The XCK pin is only active when using Synchronous mode.Figure 19-2 shows a block diagram of the clock generation logic.8155C–AVR–02/11149

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