ATmega32A Datasheet - Sunrom Technologies

ATmega32AFigure 19-1. USART Block Diagram (1)Clock GeneratorUBRR[H:L]OSCBAUD RATE GENERATORSYNC LOGICPINCONTROLXCKTransmitterDATABUSUDR (Transmit)TRANSMIT SHIFT REGISTERPARITYGENERATORTXCONTROLPINCONTROLReceiverTxDCLOCKRECOVERYRXCONTROLRECEIVE SHIFT REGISTERDATARECOVERYPINCONTROLRxDUDR (Receive)PARITYCHECKERUCSRA UCSRB UCSRCNote: 1. Refer to Figure 1-1 on page 2, Table 12-14 on page 66, and Table 12-8 on page 61 for USARTpin placement.The dashed boxes in the block diagram separate the three main parts of the USART (listed fromthe top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.The clock generation logic consists of synchronization logic for external clock input used by synchronousslave operation, and the baud rate generator. The XCK (Transfer Clock) pin is onlyused by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serialShift Register, parity generator and control logic for handling different serial frame formats. Thewrite buffer allows a continuous transfer of data without any delay between frames. TheReceiver is the most complex part of the USART module due to its clock and data recoveryunits. The recovery units are used for asynchronous data reception. In addition to the recoveryunits, the receiver includes a parity checker, control logic, a Shift Register and a two levelreceive buffer (UDR). The receiver supports the same frame formats as the transmitter, and candetect frame error, data overrun and parity errors.8155C–AVR–02/11148