ATmega32A Datasheet - Sunrom Technologies

ATmega32A• Bit 5 – DORD: Data OrderWhen the DORD bit is written to one, the LSB of the data word is transmitted first.When the DORD bit is written to zero, the MSB of the data word is transmitted first.• Bit 4 – MSTR: Master/Slave SelectThis bit selects Master SPI mode when written to one, and Slave SPI mode when written logiczero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mastermode.• Bit 3 – CPOL: Clock PolarityWhen this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is lowwhen idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is summarizedbelow:Table 18-2.CPOL FunctionalityCPOL Leading Edge Trailing Edge0 Rising Falling1 Falling Rising• Bit 2 – CPHA: Clock PhaseThe settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) ortrailing (last) edge of SCK. Refer to Figure 18-3 and Figure 18-4 for an example. The CPHAfunctionality is summarized below:Table 18-3.CPHA FunctionalityCPHA Leading Edge Trailing Edge0 Sample Setup1 Setup Sample• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 haveno effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f osc isshown in the following table:Table 18-4.Relationship Between SCK and the Oscillator FrequencySPI2X SPR1 SPR0 SCK Frequency0 0 0 f osc /40 0 1 f osc /160 1 0 f osc /640 1 1 f osc /1281 0 0 f osc /21 0 1 f osc /81 1 0 f osc /321 1 1 f osc /648155C–AVR–02/11144