ATmega32A Datasheet - Sunrom Technologies

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<strong>ATmega32A</strong>The following code examples show how to initialize the SPI as a Slave and how to perform asimple reception.Assembly Code Example (1)SPI_SlaveInit:; Set MISO output, all others inputldi r17,(1
<strong>ATmega32A</strong>18.3 SS Pin Functionality18.3.1 Slave ModeWhen the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS isheld low, the SPI is activated, and MISO becomes an output if configured so by the user. Allother pins are inputs. When SS is driven high, all pins are inputs except MISO which can be userconfigured as an output, and the SPI is passive, which means that it will not receive incomingdata. Note that the SPI logic will be reset once the SS pin is driven high.The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronouswith the master clock generator. When the SS pin is driven high, the SPI Slave will immediatelyreset the send and receive logic, and drop any partially received data in the Shift Register.18.3.2 Master ModeWhen the SPI is configured as a Master (MSTR in SPCR is set), the user can determine thedirection of the SS pin.18.3.3 SPCR – SPI Control RegisterIf SS is configured as an output, the pin is a general output pin which does not affect the SPIsystem. Typically, the pin will be driving the SS pin of the SPI Slave.If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pinis driven low by peripheral circuitry when the SPI is configured as a Master with the SS pindefined as an input, the SPI system interprets this as another master selecting the SPI as aslave and starting to send data to it. To avoid bus contention, the SPI system takes the followingactions:1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result ofthe SPI becoming a slave, the MOSI and SCK pins become inputs.2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREGis set, the interrupt routine will be executed.Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possibilitythat SS is driven low, the interrupt should always check that the MSTR bit is still set. If theMSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI mastermode.Bit 7 6 5 4 3 2 1 0SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCRRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 0• Bit 7 – SPIE: SPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the ifthe global interrupt enable bit in SREG is set.• Bit 6 – SPE: SPI EnableWhen the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPIoperations.8155C–AVR–02/11143
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ATmega32A2. OverviewThe Atmel ® AV
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ATmega32Ametrical drive characteris
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ATmega32A6.3.1 SREG - AVR Status Re
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ATmega32A6.4.1 The X-register, Y-re
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ATmega32AFigure 6-5.Single Cycle AL
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ATmega32AA return from an interrupt
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ATmega32AFigure 7-2.Data Memory Map
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ATmega32AEEPROM data corruption can
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ATmega32ASupport - Read-While-Write
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ATmega32AThe next code examples sho
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ATmega32A8.1.3 Flash Clock - clk FL
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ATmega32AThe CKSEL0 Fuse together w
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ATmega32A8.7 Calibrated Internal RC
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ATmega32A8.10 Register Description8
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ATmega32Aface, Timer/Counters, Watc
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ATmega32A9.8.4 Internal Voltage Ref
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ATmega32A10. System Control and Res
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ATmega32AFigure 10-3.MCU Start-up,
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ATmega32AADC is used. To reduce pow
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ATmega32AThe WDP2, WDP1, and WDP0 b
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ATmega32Athe case if the Reset Vect
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ATmega32A$382D out SPL,r16$382E sei
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ATmega32A12. I/O Ports12.1 Overview
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ATmega32AIf PORTxn is written logic
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ATmega32AThe following code example
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ATmega32AFigure 12-5. Alternate Por
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ATmega32ATable 12-3.Table 12-4 and
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ATmega32A• MOSI - Port B, Bit 5MO
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ATmega32A12.3.3 Alternate Functions
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ATmega32ATable 12-11. Overriding Si
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ATmega32A12.4.13 PIND - Port D Inpu
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ATmega32Alow level interrupt is sel
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ATmega32A14. 8-bit Timer/Counter0 w
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ATmega32ASignal description (intern
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ATmega32Athe OCR0 value, the compar
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ATmega32AFigure 14-5.CTC Mode, Timi
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ATmega32AThe PWM resolution for the
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ATmega32AFigure 14-9. Timer/Counter
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ATmega32ATable 14-2. Waveform Gener
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ATmega32AThe Output Compare Registe
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ATmega32AFigure 15-1.T1/T0 Pin Samp
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Page 95 and 96: ATmega32Athe main code and the inte
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Page 99 and 100: ATmega32AThe ICR1 Register can only
Page 101 and 102: ATmega32ARegister to either TOP or
Page 103 and 104: ATmega32AA change of the COM1x1:0 b
Page 107: ATmega32AThe PWM resolution for the
Page 110: ATmega32AUsing the ICR1 Register fo
Page 113 and 114: ATmega32ATable 16-3 shows the COM1x
Page 115 and 116: ATmega32A• Bit 7 - ICNC1: Input C
Page 117 and 118: ATmega32AThe Input Capture is updat
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Page 121 and 122: ATmega32AFigure 17-2.DATA BUSCounte
Page 123 and 124: ATmega32AThe setup of the OC2 shoul
Page 125 and 126: ATmega32AFigure 17-5.CTC Mode, Timi
Page 127 and 128: ATmega32A17.7.4 Phase Correct PWM M
Page 129 and 130: ATmega32AFigure 17-9. Timer/Counter
Page 131 and 132: ATmega32A• If Timer/Counter2 is u
Page 133 and 134: ATmega32AA FOC2 strobe will not gen
Page 135 and 136: ATmega32A17.11.2 TCNT2 - Timer/Coun
Page 137 and 138: ATmega32A17.11.7 SFIOR - Special Fu
Page 139 and 140: ATmega32Acommunication cycle when p
Page 141: ATmega32AAssembly Code Example (1)S
Page 145 and 146: ATmega32A18.3.4 SPSR - SPI Status R
Page 147 and 148: ATmega32A19. USART19.1 Features19.2
Page 149 and 150: ATmega32A19.2.1 AVR USART vs. AVR U
Page 151 and 152: ATmega32ATable 19-1.Operating ModeA
Page 153 and 154: ATmega32AThe frame format used by t
Page 155 and 156: ATmega32AThe following code example
Page 157 and 158: ATmega32AThe Transmit Complete (TXC
Page 159 and 160: ATmega32AAssembly Code Example (1)U
Page 161 and 162: ATmega32AThe PE bit is set if the n
Page 163 and 164: ATmega32AFigure 19-7.Stop Bit Sampl
Page 165 and 166: ATmega32AIf the receiver is set up
Page 167 and 168: ATmega32AThe following code example
Page 169 and 170: ATmega32A• Bit 0 - MPCM: Multi-pr
Page 171 and 172: ATmega32ATable 19-6.USBS Bit Settin
Page 173 and 174: ATmega32ATable 19-9.BaudRate(bps)Ex
Page 175 and 176: ATmega32ATable 19-11.BaudRate(bps)E
Page 177 and 178: ATmega32A20. Two-wire Serial Interf
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Page 181 and 182: ATmega32AFigure 20-6.Typical Data T
Page 183 and 184: ATmega32AFigure 20-9.Overview of th
Page 185 and 186: ATmega32A20.6 Using the TWIThe AVR
Page 187 and 188: ATmega32AAssembly code example C ex
Page 189 and 190: ATmega32ATable 20-2.Status Code(TWS
Page 191 and 192: ATmega32AFigure 20-12. Formats and
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ATmega32ATable 20-3.Status Code(TWS
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ATmega32AThe upper seven bits are t
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ATmega32AFigure 20-16. Formats and
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ATmega32ATable 20-5.Status Code(TWS
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ATmega32A4. The transfer must be fi
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ATmega32A20.9.2 TWCR - TWI Control
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ATmega32A20.9.5 TWAR - TWI (Slave)
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ATmega32A22. Analog to Digital Conv
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ATmega32AIf differential channels a
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ATmega32Ain ADCSRA. The prescaler k
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ATmega32ATable 22-1.ConditionADC Co
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ATmega32AIf the user has a fixed vo
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ATmega32AFigure 22-9.ADC Power Conn
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INLATmega32AFigure 22-12. Integral
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ATmega32ATable 22-2.Correlation bet
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ATmega32ATable 22-4.MUX4:011010 ADC
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ATmega32A22.9.4 SFIOR - Special Fun
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ATmega32A• TMS: Test Mode Select.
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ATmega32AThe TMS input must be held
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ATmega32A23.8 Using the JTAG Progra
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ATmega32A24.3.1 Bypass RegisterThe
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ATmega32AThe active states are:•
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ATmega32AFigure 24-4. General Port
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ATmega32AFigure 24-7.Boundary-scan
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ATmega32ATable 24-4.SignalNameBound
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ATmega32ATable 24-5.SignalNameBound
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ATmega32ATable 24-6.Algorithm for U
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ATmega32ATable 24-7. ATmega32A Boun
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ATmega32ATable 24-7. ATmega32A Boun
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ATmega32A25. Boot Loader Support -
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ATmega32AFigure 25-1.Read-While-Wri
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ATmega32Amemory by SPM instruction.
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ATmega32ANotes: 1. The different va
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ATmega32A25.8.8 EEPROM Write Preven
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ATmega32Asbiw loophi:looplo, 2brne
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ATmega32A26. Memory Programming26.1
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ATmega32ATable 26-4.Fuse Low ByteFu
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ATmega32ATable 26-7.Signal Name inP
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ATmega32Achanged. A Chip Erase must
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ATmega32AFigure 26-3. Programming t
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ATmega32A3. Set BS1 to “0” and
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ATmega32A26.7.14 Parallel Programmi
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ATmega32A26.9 SPI Serial Programmin
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ATmega32Awithout chip erasing the d
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ATmega32A26.9.4 SPI Serial Programm
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ATmega32A• Update-DR: The program
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ATmega32AFigure 26-14. Programming
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ATmega32AFigure 26-15. JTAG Program
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ATmega32AFigure 26-17. Virtual Flas
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ATmega32A26.10.18 Reading the Flash
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ATmega32A27. Electrical Characteris
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ATmega32A27.3 Speed GradesFigure 27
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ATmega32Aantees that a Brown-out Re
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ATmega32ATable 27-3. SPI Timing Par
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ATmega32ATable 27-5. ADC Characteri
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ATmega32A28. Typical Characteristic
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ATmega32AFigure 28-4.Active Supply
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ATmega32AFigure 28-8.Idle Supply Cu
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ATmega32AFigure 28-12. Idle Supply
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ATmega32A28.5 Standby Supply Curren
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ATmega32AFigure 28-20. Reset Pull-u
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ATmega32AFigure 28-24. I/O Pin Sink
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ATmega32AFigure 28-28. Reset Input
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ATmega32AFigure 28-32. BOD Threshol
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ATmega32AFigure 28-36. Calibrated 8
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ATmega32AFigure 28-48. ADC Current
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ATmega32A28.12 Current Consumption
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ATmega32A29. Register SummaryAddres
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ATmega32A30. Instruction Set Summar
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ATmega32AMnemonics Operands Descrip
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ATmega32A32. Packaging Information3
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ATmega32A32.3 44M1DMarked Pin# 1 ID
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ATmega32A34. Datasheet Revision His
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ATmega32A8.9 Timer/Counter Oscillat
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ATmega32A18.2 Overview ............
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ATmega32A26 Memory Programming ....
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Atmel Corporation2325 Orchard Parkw
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ATmega32A Datasheet - Sunrom Technologies

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