ATmega32A Datasheet - Sunrom Technologies

ATmega32AA FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode usingOCR2 as TOP.The FOC2 bit is always read as zero.• Bit 6, 3 – WGM2[1:0]: Waveform Generation ModeThese bits control the counting sequence of the counter, the source for the maximum (TOP)counter value, and what type of waveform generation to be used. Modes of operation supportedby the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, andtwo types of Pulse Width Modulation (PWM) modes. See Table 17-2 and “Modes of Operation”on page 124.Table 17-2. Waveform Generation Mode Bit Description (1)ModeWGM21(CTC2)WGM20(PWM2)Timer/Counter Mode ofOperationNote: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.However, the functionality and location of these bits are compatible with previous versions ofthe timer.• Bit 5:4 – COM2[1:0]: Compare Match Output ModeThese bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bitsare set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be setin order to enable the output driver.When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0bit setting. Table 17-3 shows the COM21:0 bit functionality when the WGM21:0 bits are set to anormal or CTC mode (non-PWM).Table 17-3. Compare Output Mode, non-PWM ModeTOPUpdate ofOCR20 0 0 Normal 0xFF Immediate MAXTOV2 FlagSet on1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM2 1 0 CTC OCR2 Immediate MAX3 1 1 Fast PWM 0xFF BOTTOM MAXCOM21 COM20 Description0 0 Normal port operation, OC2 disconnected.0 1 Toggle OC2 on compare match1 0 Clear OC2 on compare match1 1 Set OC2 on compare match8155C–AVR–02/11133