ATmega32A Datasheet - Sunrom Technologies
ATmega32A Datasheet - Sunrom Technologies ATmega32A Datasheet - Sunrom Technologies
ATmega32A16.7 Compare Match Output UnitThe Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator usesthe COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 16-5 shows a simplifiedschematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/Opins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to theOC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Resetoccur, the OC1x Register is reset to “0”.Figure 16-5.Compare Match Output Unit, SchematicCOMnx1COMnx0FOCnxWaveformGeneratorDQOCnx10OCnxPinDQDATABUSPORTDQDDRclk I/OThe general I/O port function is overridden by the Output Compare (OC1x) from the WaveformGenerator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output)is still controlled by the Data Direction Register (DDR) for the port pin. The Data DirectionRegister bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visibleon the pin. The port override function is generally independent of the Waveform Generationmode, but there are some exceptions. Refer to Table 16-2, Table 16-3 and Table 16-4 fordetails.The design of the output compare pin logic allows initialization of the OC1x state before the outputis enabled. Note that some COM1x1:0 bit settings are reserved for certain modes ofoperation. See “Register Description” on page 112.The COM1x1:0 bits have no effect on the Input Capture unit.16.7.1 Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on theOC1x Register is to be performed on the next compare match. For compare output actions in thenon-PWM modes refer to Table 16-2 on page 112. For fast PWM mode refer to Table 16-3 onpage 113, and for phase correct and phase and frequency correct PWM refer to Table 16-4 onpage 113.8155C–AVR–02/11102
ATmega32AA change of the COM1x1:0 bits state will have effect at the first compare match after the bits arewritten. For non-PWM modes, the action can be forced to have immediate effect by using theFOC1x strobe bits.16.8 Modes of OperationThe mode of operation, that is, the behavior of the Timer/Counter and the output compare pins,is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Outputmode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM outputgenerated should be inverted or not (inverted or non-inverted PWM). For non-PWM modesthe COM1x1:0 bits control whether the output should be set, cleared or toggle at a comparematch (See “Compare Match Output Unit” on page 102.)For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 110.16.8.1 Normal ModeThe simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the countingdirection is always up (incrementing), and no counter clear is performed. The counter simplyoverruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from theBOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set inthe same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaveslike a 17th bit, except that it is only set, not cleared. However, combined with the timer overflowinterrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software.There are no special cases to consider in the Normal mode, a new counter value can bewritten anytime.The Input Capture unit is easy to use in Normal mode. However, observe that the maximuminterval between the external events must not exceed the resolution of the counter. If the intervalbetween events are too long, the timer overflow interrupt or the prescaler must be used toextend the resolution for the capture unit.The output compare units can be used to generate interrupts at some given time. Using the outputcompare to generate waveforms in Normal mode is not recommended, since this will occupytoo much of the CPU time.16.8.2 Clear Timer on Compare Match (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Registerare used to manipulate the counter resolution. In CTC mode the counter is cleared to zero whenthe counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. Thismode allows greater control of the compare match output frequency. It also simplifies the operationof counting external events.The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNT1)increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)is cleared.8155C–AVR–02/11103
- Page 52 and 53: ATmega32AIf PORTxn is written logic
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<strong>ATmega32A</strong>16.7 Compare Match Output UnitThe Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator usesthe COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 16-5 shows a simplifiedschematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/Opins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to theOC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Resetoccur, the OC1x Register is reset to “0”.Figure 16-5.Compare Match Output Unit, SchematicCOMnx1COMnx0FOCnxWaveformGeneratorDQOCnx10OCnxPinDQDATABUSPORTDQDDRclk I/OThe general I/O port function is overridden by the Output Compare (OC1x) from the WaveformGenerator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output)is still controlled by the Data Direction Register (DDR) for the port pin. The Data DirectionRegister bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visibleon the pin. The port override function is generally independent of the Waveform Generationmode, but there are some exceptions. Refer to Table 16-2, Table 16-3 and Table 16-4 fordetails.The design of the output compare pin logic allows initialization of the OC1x state before the outputis enabled. Note that some COM1x1:0 bit settings are reserved for certain modes ofoperation. See “Register Description” on page 112.The COM1x1:0 bits have no effect on the Input Capture unit.16.7.1 Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on theOC1x Register is to be performed on the next compare match. For compare output actions in thenon-PWM modes refer to Table 16-2 on page 112. For fast PWM mode refer to Table 16-3 onpage 113, and for phase correct and phase and frequency correct PWM refer to Table 16-4 onpage 113.8155C–AVR–02/11102
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