A Statistical Reliability Model for Single-Electron ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008 1547A Statistical Reliability Model forSingle-Electron Threshold LogicChunhong Chen, Senior Member, IEEE, and Yanjie MaoAbstract—As one of the most promising candidates for futuredigital circuit applications, single-electron tunneling (SET) technologyhas been used to ensure further feature size reductionand ultralow power dissipation. However, this technology raisesvery serious concerns about reliable functioning, particularly dueto random background charges and tight fabrication tolerances.Accurate evaluation of reliability for SET circuits has thus becomea crucial step toward their reliability analysis and improvement.This brief proposes a statistical reliability model for SET logicgates, which takes into account the actual process variations andinput probabilities. In particular, we study two typical SET logicgates (two-input NOR and NAND gates) for gate reliability evaluation.Instead of assuming a constant failure rate for logic gatesas in most previous work, we show how logic inputs affect thereliability of the individual gates with discussions on the overallreliability of the system consisting of logic gates. This model can beused in future computer-aided design tools to estimate tunnelingevents, energy consumption, and reliability of SET-based digitallogic circuits.Index Terms—Nanoelectronics, reliability modeling, singleelectrondevices, threshold logic gates.I. INTRODUCTIONWHILE CMOS technology has been the main streamfor microelectronic systems in the past few decades, itseems to reach its limit of physical dimension in the foreseeablefuture. In order to obtain further reduction in device size andultralow power dissipation, various emerging nanometer-scaletechnologies have been studied, such as single-electron tunneling(SET) technology, carbon nanotubes (CNTs), and quantumdotautomata (QCA). However, with nanoscale devices that aremore sensitive to a variety of random noises, nanoelectroniccircuits are statistically less reliable than traditional CMOScounterparts. This makes reliability one of the biggest concernsin designing practical nanosystems.Progress in research work on reliability issues of nanoelectroniccircuits involves two aspects: 1) reliability analysis/evaluation and 2) improvement. Reliability analysis refers totechniques for estimating circuit reliability and/or finding acceptableerror bounds of individual devices for reliable operationof the overall circuit. Among these techniques are theMarkov model [1], Markov random fields [2], the BayesianManuscript received January 10, 2008; revised March 18, 2008. This workwas supported in part by the Natural Sciences and Engineering ResearchCouncil of Canada under Grant 249499-06. The review of this brief wasarranged by Editor M. Reed.The authors are with the Department of Electrical and Computer Engineering,University of Windsor, Windsor, ON N9B 3P4, Canada (e-mail:cchen@uwindsor.ca).Digital Object Identifier 10.1109/TED.2008.922856formalism [3], the probabilistic transfer matrix (PTM) [4],the probabilistic gate model, and the bifurcation method [6].More recently, reliability analysis considering the effects ofinternal parameter variations on individual gates was also presented[18]. However, most of the previous work on reliabilityanalysis is analytical in nature and, thus, is unlikely to capturethe impact of one logic module’s reliability on the subsequentmodules.Reliability improvement, on the other hand, involves theuse of various techniques for increased reliability. From thecircuit designers’ point of view, the following approaches canbe used to improve the reliability of circuits with unreliablenanodevices.1) For a given logic structure, different circuit parameterslead to different reliabilities. This provides room forreliability improvement [19].2) Instead of using traditional digital signal representation(i.e., logic low or high are defined as discrete voltage/charge levels), one can introduce a new informationencoding (such as entropy) to make the circuits lesssensitive to random noises [2], [20].3) Some research work focus on fault-tolerant circuit architecturesusing redundancy [7], [21]–[25], most of whichare an extended study of von Neumann’s multiplexingtheory on majority and NAND gates.In the first approach, the reliability improvement has beenshown to be very limited. While method 2 looks promising,it seems to be complicated and hard to implement with nanotechnology.For method 3, research shows that a low failurerate for each individual gate is required, and a high degree ofredundancy is normally needed. However, the availability of alarge number of devices on chip suggests that the redundancystrategy is still one of the best solutions in dealing with reliabilityproblem. This is one of the reasons behind why most of thecurrent literature is focusing on redundant architectures.This brief evaluates the reliability of SET-based logic gatesby presenting a statistical model that takes into account avariety of parameter variations. Generally speaking, the sourceof variations or fluctuations depends on technology being usedfor implementing a logic gate. In the case of CMOS technology,one may consider MOSFETs’ threshold voltage, powersupply, temperature, physical size variations of transistors, andother random noises. In this brief, we will focus on singleelectronthreshold logic where the main fluctuations comefrom capacitances, input signal levels, and, particularly, randombackground charges. Previous work assumes a constant failurerate of individual gates, which is simply not the case, as will0018-9383/$25.00 © 2008 IEEE

1548 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008be shown later in this brief. The significance of the proposedmodel includes: 1) indication that the reliability of a gate isnot independent of other gates in the circuit but is affected byall its fan-ins, and that the reliability propagates through thecircuit in different ways than traditional methods; 2) ability toset up the relationship between process variations and the errorbound for reliable operations, which serves as an importantguideline for circuit designers; and 3) its general applicabilityto other logic gates and other nanoscale technologies whileour discussions are given on SET-based two-input NOR andNAND logic gates only. SET threshold logic uses a net chargeof zero or one electron as logic values because it is designed insuch a way that the output voltage change is appreciable withand without electron tunneling. The proposed model applies toother SET digital logic families as long as they are based onvoltage mode, such as SET transistor logic, SET BDD logic,and SET programmable logic.It is worth noting that our discussions throughout this briefare based on the orthodox theory that ignores cotunneling(as a second-order effect) involved in the tunnel junctions ofSET-based logic gates. It has been recognized that cotunnelingcan play an important role in the real-world environmentand require precise quantum mechanical analysis. Researchshows, however, that cotunneling events are generally veryrare processes compared to a normal tunnel event [14], particularlyin situations where only one or few tunnel junctionsare involved, as is the case for individual gate modeling to bediscussed.Fig. 1. Generic SET-based threshold logic gate (from [11]).II. STATISTICAL RELIABILITY MODELFOR INDIVIDUAL GATESA variety of nanoscale devices are currently being used todesign digital logic. SET devices are such an example, wherethe Boolean logic values 0 and 1 are encoded as net chargesof zero and one electron [9]–[13]. However, the random noises(such as process variations and random background charges)and physical failures with devices and interconnects may leadto faulty logic behaviors. When this happens with a wrong logicoutput, the logic gate/circuit is said to fail. If a logic gate hasa failure probability ε, it is said to have a reliability r, wherer = 1 − ε. The failures due to random noises are generallycalled “soft errors,” while those caused by physical defects arenamed “hard errors.” In this section, we will use two-inputSET-based logic gates as an example to show by experimenthow the gate reliabilities depend on process variations andinput signal probabilities. For several reviews of experimentalwork on single electron phenomena, the readers are referredto related literature on this subject (e.g., [16] and [17]). Whilewe can consider all possible statistical noises, including temperatureand supply voltage variation, it is assumed in thisbrief that only soft errors caused by such process variationsas capacitance fluctuations and background charges are studiedwith special attention to input signal probabilities that maysignificantly affect the gate reliability, even for the same processvariations, as will become clear later in this section. Thus, theproposed model turns out to be approximate with statisticalnature.Fig. 2.Two-input SET-based NOR gate implementation.A. Implementation of a Two-Input NOR GateA generic SET-based threshold logic gate has been proposedin [11] and is shown in Fig. 1 for convenience of discussion.This gate, if the involved parameters are chosen properly, isable to implement a certain Boolean function [11]. In Fig. 1.assuming Y is the logic level of output voltage V o , and X asetof input voltages, we have{0, if F (X) < 0Y =sgn{F (X)} =(1)1, if F (X) ≥ 0whereF (X) =C n ΣΣ r k=1C p k V pk − Cp Σ Σs l=1C n l V nl − ϕ (2)ϕ = 1 2 (Cp Σ + Cn Σ) q e − C n ΣC b V b (3)C p Σ = C b +Σ r k=1C p kCΣ n = C o +Σ s l=1Cl n . (4)Note that q e is the fundamental charge of an electron, andmore details on the derivation of the above equations can befound in [26].As an instance of Fig. 1, a two-input NOR gate is shown inFig. 2. When 0 V and 16 mV are chosen as logic 0 and 1,respectively, the following parameter values (called standard

CHEN AND MAO: STATISTICAL RELIABILITY MODEL FOR SINGLE-ELECTRON THRESHOLD LOGIC 1549B. Experiment on the Reliability of a Two-Input NOR GateFig. 3. Simulation results of Fig. 2.values) can be used to implement NOR logic: V b = 16 mV;C 1 = C 2 = 0.5 aF; C o = 9aF;C b = 10.6 aF; C j = 1.0 aF;and R j = 100 kΩ (see [26] and [27] for the details about howto derive these parameters). Fig. 3 depicts the simulation resultsusing the simulator SIMON [14], which verify the correct logicoperation. However, the NOR gate is sensitive to process variations(such as capacitances that deviate their standard values)and random background charges on islands x and y, and it maybecome unreliable due to these random noises. Given specificvariations of all parameters in the circuit, a general sensitivityto-variationanalysis can be carried out experimentally usingMATLAB and SIMON [15].In order to see how the reliability of the above two-input NORgate depends on random noises as well as input patterns, weconduct a particular experiment with the following assumptions(the same can be done with any other gates).1) The noises from all capacitances and islands (i.e., nodesx and y in Fig. 2) are modeled as a Gaussian process withmean µ and variance σ 2 . The probability density functionof the Gaussian distribution isf(z; µ, σ) = 1 ( )σ √ 2π exp (z − µ)2−2σ 2 (5)where z is a random variable. In case of capacitances,z is the random capacitance value, with mean µ beingits standard value. In case of islands, z represents therandom background charge value, with mean µ = 0. Thevalue of σ can be selected based on the varying rangeof the random variable. If the range is ±η × 100% forcapacitances or ±η × q e for random background charges,then the value of σ can be set as follows: σ c = 1/3ηC stdfor capacitances (here, C std is the standard capacitancevalue) or σ q = ηq e /3 for random background charges.This is because, in a Gaussian distribution, 99.7% ofthe area is within three standard deviations. Here, ηis an important parameter representing the extent ofprocess variations and is, hence, called variation factorthereafter.2) The probabilities of input voltages V 1 and V 2 being logic1areP 1 and P 2 , respectively, and they are independent.The experiment is done as follows. Random fluctuations areinjected into all capacitances in the circuit and backgroundcharges q x and q y on islands x and y by using Gaussiandistribution. The circuit is then simulated with SIMON fordifferent input voltages (V 1 and V 2 ), which are also randomlygenerated based on their probabilities P 1 and P 2 . The processof varying the values and conducting simulations is repeatedfor T = 10 000 times while the data are collected. Assumingthat the number of correct outputs is M, the ratio M/T canbe used as a good estimate of the gate reliability r. Note thatthis experiment is based on the static response of the gate withthe assumption that any transient process is finished before thesimulation data are collected. Indeed, there is no guaranteethat a tunneling event would occur within a certain period,even though all conditions for tunneling are met. However,considering the fact that the error probability of a tunnelingevent is an exponential function of time delay, this probabilityis pretty close to 0 (typically around 10 −12 ∼ 10 −9 ), as long asthe delay is large enough (typically around nanoseconds) [11],and would not be considered a big concern, compared to thereliability in our discussions.The above evaluation process is repeated for different valuesof η, P 1 , and P 2 , and the gate reliability can be generallyexpressed in terms of η, P 1 , and P 2 , i.e., r = r(η, P 1 ,P 2 ).Table I shows one group of the estimated reliabilities with aspecific value of η = 0.04. Instead of reporting all data aboutthe reliabilities from our experiments, we observe from thisevaluation process the following: 1) the gate reliability r is

1550 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008TABLE IESTIMATED RELIABILITY r FOR A TWO-INPUT NOR GATE WITH η = 0.04reduced, as expected, when the value of η increases; 2) the twoinputs of the gate are equivalent in logic, making the resultssymmetrical in terms of P 1 and P 2 , as demonstrated in Table Iwith some statistical error; and 3) the value of r is stronglydependent on P 1 and P 2 . It can also be seen from Table Ithat for this NOR gate, the highest reliability is achieved whenP 1 = P 2 = 1.The above experiment assumes a Gaussian distributionshared by both capacitances and random background chargeswith a single variation factor η. However, depending on thedevice fabrication technology, these fluctuations may have differentdistributions (such as uniform distribution) with differentstatistical parameters. In this case, more variation factors aregenerally needed during the above reliability evaluation, whilethe experimental procedure still keeps the same.C. Statistical Model for Gate ReliabilityInstead of finding out an explicit expression r = r(η, P 1 ,P 2 )which is statistically difficult, we resort to the regressionmethod as follows. For a given value of η, the two models areused for the two-input NOR gate, i.e.,orr = α 0 + α 1 (P 1 + P 2 )+α 2 P 1 P 2 (6)r = α 0 ′ + α 1(P ′ 1 + P 2 )+α 2P ′ 1 P 2 + α 3 ′ (P21 + P22 )where the coefficients α i (i = 0, 1, and 2) and α j ′ (j = 0,1, 2, and 3) are constants. To see how accurate the abovemodels are, we use the method of least squares to obtain thevalues of all coefficients in (6) and (7) with data of Table I.The results are α 0 = 0.8788, α 1 = −0.0645, and α 2 = 0.2486for the first model, with a maximum error of 0.8%, and α 0 ′ =0.8790, α 1 ′ = −0.0652, α 2 ′ = 0.2485, and α 3 ′ = 0.0007 for thesecond model, with a maximum error of 0.79%. Throughoutthis brief, the first model is used because it is simpler and is ingood agreement with the experimental data.(7)When taking into account the role of η, the first model can begenerally rewritten asr = r(η, P 1 ,P 2 )=α 0 (η)+α 1 (η)(P 1 + P 2 )+α 2 (η)P 1 P 2(8)where α 0 (η), α 1 (η), and α 2 (η) can be obtained using the aboveexperiments.D. Reliability Model for Other GatesThe similar experiment can be conducted for any type ofgates with multiple inputs. For instance, a two-input NAND gatecan also be implemented using Fig. 2 with different parameters:V b = 16 mV; C 1 = C 2 = 0.5 aF; C o = 9aF;C b = 11.8 aF;C j = 1.0 aF; and R j = 100 kΩ. By performing the reliabilityexperiment, we observe similar properties of the reliability r,except that with a NAND gate, the value of r reaches maximumwhen P 1 = P 2 = 0 for any given variation factor η. Therefore,a similar reliability model can be used for the two-input NANDgate, i.e.,r = r(η, P 1 ,P 2 )=β 0 (η)+β 1 (η)(P 1 + P 2 )+β 2 (η)P 1 P 2(9)where the coefficients β 0 (η), β 1 (η), and β 2 (η) can be obtainedagain through the experiments.In general, for K-input gates, the statistical reliability modelcan be approximately expressed asr = r(η, P 1 ,P 2 ,...,P K )= γ 0 (η)+γ 1 (η)K∑P i + γ 2 (η)i=1K∑i,j,j>iP i P j (10)with the coefficients γ 0 (η), γ 1 (η) ,and γ 2 (η) to be determinedstatistically by the experiments.

CHEN AND MAO: STATISTICAL RELIABILITY MODEL FOR SINGLE-ELECTRON THRESHOLD LOGIC 1551III. RELIABILITY ANALYSIS FORSET-BASED LOGIC CIRCUITSIt is straightforward that if the variation factor η of anindividual gate increases, its reliability would be reduced, andthe circuit with these gates may eventually become much unreliable.Given the above reliability models, a natural questionto ask is: For what value of variation factor η can the circuitconsisting of individual gates operate reliably in a probabilisticsense? This similar question has been answered through bifurcationanalysis [6] if the failure rate of an individual gate isa constant ε. In [6], it was found theoretically that the errorbound for a NAND gate is ε ∗ = 0.08856. In other words, theindividual NAND gate should have a reliability no smaller thanr ∗ = 1 − ε ∗ = 0.91144 for the circuit built out of NAND gatesto compute reliably with probability greater than 1/2. However,the assumption of a constant reliability in the circuit is unrealistic.This is because the reliability of a specific logic gate in thecircuit, along with its input probabilities, determines its outputprobability, which, as indicated in our statistical model, willchange the reliability of its fan-out gates. More specifically, thesame NAND gates in the circuit may have different reliabilitiesdue to the varying probabilities at their inputs, and all theseprobabilities and reliabilities can also propagate throughout thecircuit from its inputs to outputs.Generally speaking, for realistic circuits, one can simply use(8)–(10) to calculate the individual gate’s reliability from primaryinputs to outputs. The problem is that in order to evaluatethe overall reliability of the system (by which we mean whetherthe system can operate reliably in a probabilistic sense), oneneeds to assume all possible signal probabilities at the inputswhen using the above equations, which is computationallyvery expensive. However, with the bifurcation approach, whichrepresents a worst-case scenario [6], the efficiency can besignificantly improved. In other words, the bifurcation analysisis independent of input probabilities, while the reliabilitycalculation for specific circuits is not. Any analysis on specificcircuits using particular input probabilities gives no informationabout the reliability of the circuit. In this section, we will applythe bifurcation technique when the individual gate reliability ris not a constant.A. Bifurcation Analysis for Circuits Built Out of NOR GatesAssuming that the two inputs of a NOR gate are independent,with probabilities P 1 and P 2 of their logic values being “1,” theprobability P o of the output V o being “1” isP 0 = r(1 − P 1 )(1 − P 2 )+(1 − r){(1 − (1 − P 1 )(1 − P 2 ))(11)where r is the reliability of the gate, given by (8).For bifurcation analysis, let P 1 = P 2 = X n , and P 0 =X n+1 . Combining (8) and (11) leads to a nonlinear mappingfunction, which is described byX n+1 = f(X n )= { α 0 (η)+2α 1 (η)X n +α 2 (η)Xn2 }(1−Xn ) 2+ { 1−α 0 (η)−2α 1 (η)X n −α 2 (η)Xn}( 2 2Xn −Xn) 2 .(12)Fig. 4.Gate reliability at different stages of a NOR-gate circuit.The bifurcation procedure works numerically as follows. Ifone chooses an initial value of the bifurcation parameter η,then X n in (12) converges to x 0 . When |f ′ (x 0 )| > 1, x 0 losesstability. In other words, the system computes reliably in aprobabilistic sense. This is because of the fact that for a twoinputNOR gate to function reliably, two identical inputs of “1”or “0” should output a “0” or “1,” respectively. Indeed, whenη is very small, the gate has a high reliability, and it is foundthat |f ′ (x 0 )| > 1, indicating that the system is reliable. As ηgradually increases, one can keep checking if |f ′ (x 0 )| > 1forany solution x 0 to (12). Eventually, at η = η ∗ , |f ′ (x 0 )| = 1.That is when the system fails to compute reliably. This behaviorcan be interpreted as follows. Any circuit built out of two-inputNOR gates with η

1552 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 6, JUNE 2008B. Bifurcation Analysis for Circuits Built Out of NAND GatesAssuming that the two inputs of a NAND gate are independent,with probabilities P 1 and P 2 of their logic values being“1,” the probability P o of the output V o being “1” isP 0 = r(1 − P 1 P 2 )+(1 − r)P 1 P 2 (13)where r is given by (9). Using similar bifurcation analysis, onecan have the following nonlinear mapping function:X n+1 = g(X n )= { β 0 (η)+2β 1 (η)X n + β 2 (η)Xn2 }( )1 − X2n+ { 1 − β 0 (η) − 2β 1 (η)X n − β 2 (η)Xn} 2 X2n . (14)Our computation reveals that for a system built out of twoinputNAND gates, η ∗ = 0.0358, x 0 = 0.6062 (with |g ′ (x 0 )| =1), β 0 = 1.0000, β 1 = −0.1093, and β 2 = 0.0893. It is interestingto see that at η = η ∗ = 0.0358, the average reliabilityover all possible input probabilities of the NAND gate canbe obtained from (9) and is found to be r avg = r ∗ = 0.8960,compared to the traditional reliability bound of 1 − ε ∗ = 1 −0.08856 = 0.91144 where ε ∗ is the error threshold given byGao et al. [6], with the assumption of a constant failurerate ε for the two-input NAND gate.C. Reliability Analysis for Circuits With Various GatesThe above bifurcation analysis assumes that the inputs of agate are statistically independent. However, this assumption isgenerally invalid for the circuit built with both NOR and NANDgates and other gates, where the input signals of a gate may becorrelated. In this case, calculation of their joint and conditionalprobabilities among the inputs is generally required before theoutput probability can be evaluated [5]. The PTMs proposedin [4] can be used to address this issue. The only differenceis that in our situations, the reliability is not a constant, but afunction of input probabilities, as shown in (8) and (9). Sincethe PTM approach is based on an exhaustive listing of inputand output probabilities, the computational cost could be veryexpensive for large circuits. A more efficient mechanism basedon Bayesian networks has been reported [3] to deal with thissituation.It should also be mentioned that in the real world, somebuffers may be needed when logic gates are cascaded, dependingon specific application circuits. Fortunately, when the capacitanceparameters of a SET threshold logic gate are carefullychosen, one can limit the capacitive influence when multiplegates cascaded. Typically, the output capacitance C o (see Fig. 1)is selected to be much larger than other capacitors, resultingin low input capacitance and high output capacitance [26].While our focus is on general circuits with NAND and NORgates without buffers, the proposed model does apply to thebuffers if they are actually needed. The only difference is thatthe bifurcation analysis cannot be performed directly to thecircuit with both NAND/NOR gates and buffers, since they havedifferent mapping functions. A possible solution is to do thebifurcation analysis for regular gates and for buffers separatelyin order to find their error bounds, the smaller of which servesas the actual error bound of the circuit.IV. FURTHER WORK AND APPLICATIONThe proposed model characterizes a SET-based logic gatein terms of reliability and can be used not only for the wholecircuit reliability analysis, but also for tunneling event analysisand energy estimation. From (11) and (13), the probability forthe tunneling event inside a gate j to occur (P t,j ) depends on itsinput probability as well as reliability, both of which are closelyinterwoven with other gates and may propagate throughout acircuit from its inputs to its outputs. The energy consumedby a single tunneling event can be calculated as ∆E j =q e (|V j |−V c ), where V j is the voltage across the junction, andV c is the critical voltage of the junction. Thus, the sum ofthe products of P t,j and ∆E j (i.e., ΣP t,j ∆E j ) over all tunnelsgives an estimated energy consumption of the SET-basedlogic circuit. The detailed implementation of this idea shall beinvestigated in our future research work.Further work is also needed to further discuss multiple-inputlogic gates and their characterization in terms of reliability andto perform bifurcation analysis and/or reliability analysis ingeneral.V. CONCLUSIONWe have proposed a statistical reliability model for individualSET logic gates. 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