A high precision method for measuring very small capacitance ...

REVIEW OF SCIENTIFIC INSTRUMENTS VOLUME 70, NUMBER 8 AUGUST 1999A high precision method for measuring very small capacitance changesAshkan Ashrafi and Hossein GolnabiInstitute of Water and Energy, Sharif University of Technology, 8639 Tehran, IranReceived 26 January 1999; accepted for publication 5 May 1999A novel method for measuring very small capacitance changes based on capacitance-to-phase angleconversion is introduced in this article. This new method is the improved or linearized version of thenonlinear capacitance-to-phase angle conversion method. The main features of this scheme are thevery good linearity, extremely high stray immunity and a very high resolution. The experimentalresults of the prototype version of this scheme have also been reported. By using this prototype anda simple capacitive transducer, a minimum detectable distance of about 16 nm can be achieved. Thismeans that a capacitance change of about 0.7 fF (0.710 15 F) in a capacitance of 22 pF can beresolved, so the minimum resolvable relative capacitance is about 32 ppm. By the theory it can beseen that the minimum resolvable relative capacitance of 2 ppm could be achieved by this method.© 1999 American Institute of Physics. S0034-67489903808-3I. INTRODUCTIONDuring the past years capacitive transducers have foundmany applications. For measuring a very small capacitancechange there is a demand for a reliable high precision readoutcircuit. In principle, measuring small capacitance changeis not a new problem. Several attempts have been made inorder to achieve high resolution measurement. These attemptsare generally based on: the ac bridge method, 1capacitance-to-frequency conversion, 1,2 and charge and dischargemethods. 3,4 Also, recently the new methods based onthe switched-capacitor technique 5,6 and capacitance-to-phaseangle conversion 7 have been reported.In this article a new method based on a linearcapacitance-to-phase angle conversion is introduced. Themain idea has been described previously, 7 but the techniquethat has been developed has several limitations and disadvantages.At first, we make some comments on these disadvantagesand then describe the modifications that have led tothe new method. By this method very small capacitancechanges can be measured with the extremely high immunityto grounded stray capacitances. In the following sections,first the theoretical description of the proposed method ispresented. Then, the experimental results of a prototype versionare given in order to demonstrate the practical implementationof the new method. Ultimately, we discuss thepractical limitations that can somehow restrict the performanceof the readout circuit.II. THEORETICAL ANALYSISA. Comments on the previous schemeFigure 1 shows the scheme offered in the previouswork. 7 This scheme has three major drawbacks, which aredescribed as follows:1 The relationship between the output phase and theinput capacitance changes is nonlinear. This relationship is inthe form of tan 1 as given in Ref. 7.2 The input impedance of the charge amplifier used inRef. 7 is not low enough for high stray-immune measurements.By assuming R f C f 1 and the input impedanceof the charge amplifier shown in Fig. 1 can be writtenas1Z in A•C f S 1 1,GS •C GC ffSwhere is the first pole of the op-amp, G is the gainbandwidthproduct of the op-amp, and R f and C f are thefeedback resistor and capacitor, respectively. In order to decreaseZ in , according to Eq. 1 we need to increase theproduct value of GC f , which can be done by increasingeither G or C f . But any increase in the value of C f causes adecrease in the output signal level. On the other hand toincrease G we are forced to use a high frequency op-amp.3 The reported charge amplifier, as it is shown in Fig.1, produces a constant phase shift in the output signal thatcauses an extra nonlinear relation between the generated outputphase angle tangent and the input capacitance changes.This phase shift depends on the frequency characteristic ofthe op-amp and its value only can be reduced by using a highfrequency op-amp.B. The new schemeFor overcoming the second and the third problems of thepervious scheme, a simple parallel R – C circuit in front of abuffer amplifier is suggested Fig. 2a. The buffer amplifiermust produce no phase shift. 8 In order to achieve such acharacteristic the active feedback scheme shown in Fig. 2bis used to design a buffer amplifier. 9 Calculations show thatif the two op-amps used for constructing the buffer amplifierare closely matched, the resulting phase shift could be writtenas 9G 3, 210034-6748/99/70(8)/3483/5/$15.00 3483© 1999 American Institute of Physics

3484 Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 A. Ashrafi and H. GolnabiFIG. 1. The schematic diagram of a capacitance-to-phase angle converterreported in Ref. 7.FIG. 3. The block diagram of the phase-sensitive detectors and monitoringcircuit.where by choosing low frequency signal, the disturbingphase shift could be considerably decreased.By assuming R T C T 1, according to Fig. 2a, wecanwriteC 0 BV 0 •sintC T C 0 C XC X A•sint,3C T C 0 C Xwhere C 0 is the reference capacitor, C X is the measured capacitor,C T is the voltage dividing capacitor, and A,B are theamplitudes of the two sinusoidal signals. By using the generalformula for the summation of two sinusoidal functions,Eq. 3 can be simplified asC 0 B•sin V 0 C T C 0 C X •sin •sint4andC X AcotC 0 B•sin cot.5Figure 2a shows the possible stray capacitance, C S2 ,appearing between plate 2 of the measurand capacitor andground that is added to C T . On the other hand, it is apparentfrom Eqs. 4 and 5 that the value of C T has no effect onthe phase of the output signal and it only changes the amplitudeof the output signal. Therefore, we can argue that thisscheme has an extreme stray immunity from side 2 of theC X .For producing two input signals, A sin(t) and B sin(t), the circuit which is shown in Fig. 2c is used. Inthis circuit, first a sinusoidal signal is produced by an oscillator.This sinusoidal signal is used for generating two balancedsignals with 180° phase difference. This is accomplishedby employing two matched op-amps. 10 Then thephase of one of the signals is shifted by R 1 and C 1 by theamount of tan 1 (R 1 C 1 ). At the end, we get two signalsdefined as A sin(t) and B sin(t), where A andB are the signal’s amplitudes.In spite of the mentioned advantages, the nonlinear behavioris still present in the new scheme. This problem canbe overcome by using a conventional quadrature phase sensitivedetector PSD that provides the cotangent of the outputphase. By this configuration one can construct a linearrelationship between the input capacitance and the output ofthe PSD. The overall block diagram of this design is shownin Fig. 3. By using switching multipliers 11,12 the two dc outputsbecomeV C 2KC 0B•sinC S•cot 6andV S 2KC 0B•sinC S, 7FIG. 2. The proposed scheme for the capacitance-to-phase angle conversion.a The modified capacitance-to-phase angle converter (C S1 and C S2show the possible stray capacitances. b The buffer amplifier. c Thecircuit design for producing the two signals with an appropriate phase difference().where C S is defined as a total capacitance (C S C T C 0C X ), and K is the gain of arbitrary ac amplifier which maybe used for increasing the amplitude of V O the output of thecapacitance-to-phase angle converter. The two referencesignals for the quadrature switching PSD have been providedby converting sin(t) and cos(t) to square waves. This conversionis accomplished by using two voltage comparators asshown in Fig. 3. By dividing Eq. 6 by Eq. 7 it is evidentthatcot V CV S.8

Rev. Sci. Instrum., Vol. 70, No. 8, August 1999Small capacitance changes3485For dividing V C by V S , first, two analog-to-digital convertersADCs convert these signals to digital numbers andthen they are conveyed to a microcomputer, where the divisionprocess is performed.The reference voltages used for the ADCs are V RC andV RS corresponding to V C and V S , respectively. If the ADCshave m-bit outputs, it can be writtenD C 2 m V CV RC,D S 2 V m S,10V RSwhere D C and D S are the digital outputs of the converterscorresponding to V C and V S , respectively. From these assumptionsand using Eqs. 5, 8, 9, and 10 a linear relationshipcan be derived between the measurand capacitorC X and D C /D S . Equation 5 then becomescot D C• V RC C X AD S V RS C 0 B•sin cot. 11It can be seen from Eq. 11 that A,B, and C 0 are the onlyparameters contributing to the output results.Let C X0 be a reference value for C X and consider themeasurand of interest to be the deviation from this referencevalue, named C X1 , so thatC X C X0 C X1 .912By substituting Eq. 12 into Eq. 11, the linear relationshipconverted tocot D C• 1 D S nC X0•AC 0 B•sin cotC X1AC 0 B•sin , 13where nV RS /V RC . By adjusting A, so that it satisfies thefollowing relationship:C X0 AC 0 B•cos,Eq. 13 can be written as14D C• 1 D S n C X1•cot.15C X0By defining C X1 /C X0 the normalized capacitance ratio asthe output (D OUT ), it can be writtenD OUT C X1 tanC X0 n• D CD S.16Equation 16 is the main relationship between the normalizedcapacitance ratio and the output number D OUT , which iscomputed by a microcomputer via a proper program. Underthe condition given in Eq. 14 the effects of A, B, and C 0can be eliminated. Equation 14 also establishes the calibrationcondition for the measurements. When Eq. 14 is satisfied,the related output D OUT for C X1 0 will be zero, so thisrelation is referred to as the ‘‘zero adjustment condition.’’C. Calculation of resolutionBecause of the normalized output, it is more appropriateto develop the resolving formula for the relative capacitancemeasurements. The resolvable relative capacitance could bethen derived from Eq. 16. As it can be inferred from Eq.16, variations of the parameters , n, and the resolution ofthe ADC’s outputs (D C /D S ) could affect the overall resolvablerelative capacitance. The variations could be minimizedby using a stable phase shifter, and its variations canbe corrected by recording for each measuring step. Bychoosing a single temperature compensated voltage referencefor both DACs, the variations of V RS and V RC due to thetemperature changes is extremely low and can be ignored.By considering the mentioned descriptions the resolvablerelative capacitance can be derived by differentiating Eq.16, which results in:D OUT tann• D CD S.17The only parameter that remains effective on the resolvablerelative capacitance is the resolution of the ADCs. If eachADC generates an error of 1 least significant bit, thenD C D S 1, and for the worst case D C D S we have D CD S 2 D S.18For achieving the highest possible resolution, D S must be aslarge as possible. Therefore, our program is arranged in sucha way that D S becomes the maximum achievable value bycontrolling V RS via digital to-analog converter DAC1 Fig.3, such as an autoranged ADC. For the ADC’s with the mbit resolution, the maximum value of D S equal to 2 m thencan be written as D C 1D S2 m1 . 19If we consider 12-bit ADCs, then the achievable resolutionof dividing V C by V S is 1000 ppm full scale D C /D S 1)according to Eq. 19. By substituting Eq. 19 into Eq. 17we will haveC X1DC OUT tanX0n•2 m1 .20Although the maximum achievable resolution from ADCs inthe dividing process is 1000 ppm, according to Eq. 20 theoverall resolution of the system can be further improved byconsidering and n. On the other hand, increasing the resolutionwill decrease the dynamic range. In order to achievethe optimum performance one has to compromise betweenthe resolvable relative capacitance and the dynamic range.D. Noise analysisThe main internal noise source is the buffer amplifier.Considering the input referred noise voltages and currents ofthe two matched op-amps E n and I n , the rms value of theoutput noise can be calculated as

3486 Rev. Sci. Instrum., Vol. 70, No. 8, August 1999 A. Ashrafi and H. GolnabiE 2 0 2E 2 0 4kT I 2 2n R T 2 C 2 S R T R T C S 1 2• f . 21By using LF353, according to its data sheet the noise voltageand current of this op-amp is 25 nV/Hz and 0.01 pA/Hz,respectively. By choosing the values: R T 22 M, C S25 pF, 2 10 000 rad/s, at room temperature and at thebandwidth of 1.5 Hz corresponding to the bandwidth of thelow pass filters used in synchronous detector the rms valueof the output noise will be 48 nV.III. EXPERIMENTAL RESULTSA prototype version of the described scheme has beenconstructed by using commercial components such as theLF353 as op-amp, ICL7109 as ADCs, and the 4053 analogswitch as switching multipliers. The operating frequency waschosen at 10 kHz.For testing the prototype circuit, we constructed a simplecapacitive transducer with a Kelvin guard ring. 13 It is designedso that the distance between its plates X is muchsmaller than the radius of the plates. In this configuration thewell known relationship of the parallel plates capacitor isvalid:C• A eX ,22where A e is the effective area of the two plates, and is thepermeability of the dielectric material between the two platesair.To control the distance X precisely and to scan this transducersmoothly a high resolution stepping motor 800 stepsper revolution was coupled to a microscrew that was drivingone of the capacitor’s plates. The microscrew has a pitch of2 turns/mm, which results a displacement of 0.625 m for asingle step of the motor.In order to obtain a linear relationship between D OUTand X, we need to exchange the position of C X and C 0 in thecircuit depicted in Fig. 2a. It is assumed that XX 0 X 1 ,where X 0 is the distance in which zero adjustment has beenmade and X 1 is the deviation from X 0 . Therefore Eq. 16becomesD OUT X 1.23X 0As mentioned, Eq. 23 represents the calibration curveof the transducer that can be obtained experimentally bychanging X 1 from the initial value of X 0 and recordingD OUT . The result of such measurements has been shown inFig. 4. This curve has been obtained by setting X 00.5 mm. The slope of this line has been calculated by theleast square method which is 2.0610 3 /m. For a comparisonthe slope is also obtained by the theory (1/X 0 ) that is210 3 /m. As can be seen there is a very good agreementbetween the theory and the experiment. However, a littledifference between the theoretical and experimental resultsmay be due to the existence of the stray capacitances betweenthe two plates of the capacitive sensor. This effect isFIG. 4. Top Shows the variation of the normalized capacitance of theconstructed transducer as a function of positive displacements between itsplates (X 1 ). Bottom Shows the percentage of nonlinearity of the relateddisplacements.probably caused by the type of connections arranged for thejunctions of the plates of the capacitive sensor and the fringingeffect near the edges of the sensor.In this computations we set: 3.7°, n1 and m12number of bits of the ADCs. By substituting these valuesinto Eq. 20 the minimum resolvable relative capacitance of32 ppm is calculated. According to the resolvable relativecapacitance of about 32 ppm, the minimum detectable displacementis about 16 nm.The nonlinearity of the curve shown in Fig. 4 is less than0.5%, which mainly depends on the fluctuations of the mechanicalscanning system.The minimum measurable displacement in the capacitivesensor is the displacement which results from a voltagechange equal to the rms noise voltage in the bandwidth of theelectronic circuit. By choosing B10 V, C 0 12 pF, C S25 pF and 3.7° according to Eq. 6, 16 and 21, cotg will be 48 nV/0.2 V2.410 7 . Considering Eqs.16 and 23 it can be seen that X 1 /X 1 tan() cotg()1.510 8 or the minimum measurable displacementis 7.710 12 m. This value is much less than theminimum resolvable relative displacement achievable by thesystematic error of the system. The lower limit of the minimumresolvable relative capacitance is achieved by choosingn15 so that it will be 2 ppm. The low noise performance ofthe readout circuit permits high precision in such measurements.IV. DISCUSSIONIn Sec. II the systematic error for the readout circuit hasbeen described. Along with systematic error, there are somepractical limitations that may affect the performance of thereadout system. However, the overall performance of thetransducer is controlled in part by the measuring circuit andby the sensor as well. Therefore, some limitations are due tosensor characteristics and some are due to the readout circuit.In our case, the resolution and the overall performance of thetransducer were mainly limited by the mechanical drive sys-

Rev. Sci. Instrum., Vol. 70, No. 8, August 1999Small capacitance changes3487tem of the capacitive sensor. Practically, to meet and measuresuch a high resolutions one has to take advantage of thesmall value of capacitance changes in the integrated circuitsensors. The resolution of the readout circuit was estimatedto be about 0.044 fF 2 ppm, however for the present system,our resolution is limited to only 0.7 fF 32 ppm. Thepractical limitations of the reported readout system and theways to minimize those can be classified as follows:1 Amplitude variations of the main oscillator cause thesame variations on the two output voltages of the PSDs (V Cand V S ). Since these two voltages are divided by each other,the amplitude variations of he main oscillator do not affectthe output.2 Phase jitters of the main oscillator degrade the stabilityof the output. This effect can be decreased primarily byusing a very stable oscillator. Besides, output oversamplingleads to a very stable output.3 Since the measurand quantity converts to the phaseangle difference between the two signals, the effects of amplitudenoise and disturbances will be very small on the outputsignal of the capacitance-to-phase angle converter. Alongwith this intrinsic behavior, the phase-sensitive detectorseliminate the noise significantly. This elimination is due toPSD’s narrow pass bands around the main fundamental frequencyand its odd harmonics. 12 The nonfundamental passbands may cause an error due to the odd harmonics of theinput sinewave but, by designing a low distortion oscillatorthis effect can be minimized.4 The only stage which can increase the output noiseand unstability is ADC, since it has a dc gain. This effectcauses a limitation on n. This limitation strongly depends onthe ADC performance and the PCB design. 14,15 For furtherdecrease of the output noise, special program is prepared tooversample the outputs of the ADCs and averaging them.This method can improve the signal-to-noise ratio but, slowdown the speed of the measurements. Noise reduction obtainedby this method is proportional to the square root of thenumber of oversamplings. For achieving a good performanceone has to compromise between the output noise reductionand the response time of the scheme.5 The dielectric absorption of the capacitor may causea phase error. 16 This phenomena causes a nonlinear relationbetween the output and the capacitance changes. For minimizingthis effect capacitances with low dielectric absorptionmust be used as C T and C 0 . The sensing capacitor must havea low dielectric absorption as well; therefore using the airdielectric for the sensor is the best choice.6 In spite of the good stray immunity of the readoutcircuit, the stray capacities between the plates of the sensorand the ground may affect the performance. For connectingthe transducer to the readout circuit, two coaxial cables havebeen used so that their outer conductors have been driven, atlow impedance, with a potential essentially equal to the voltageof the inner conductor active guarding. This arrangementsignificantly reduces the effects of grounded stray capacities.Stray capacities between the two plates of the sensoralso affect the measurements, but there is no easy method toreduce its effects on the readout circuit except by reducing itsvalue. In order to reduce its value, proper connections mustbe arranged between the plates of the sensor and the coaxialcables, and such proper connections must be made betweenthe coaxial cables and the input of the readout circuit as well.On the whole this source of noise is the main source ofinstability of the output readout that degrades the resolution.Considering the sources of noise and disturbances andtaking all the necessary precautions, the output fluctuationshave been reduced to 5 ppm which is less than the effect ofthe minimum resolvable relative capacitance 32 ppm.These fluctuations manifest themselves as the instability ofthe output.1 S. M. Huang, A. L. Stott, R. G. Green, and M. S. Beck, J. Phys. E 21, 2421988.2 F. Krummenacher, IEEE J. Solid-State Circuits SC-20, 6661985.3 S. M. Huang, R. G. Green, A. Plaskowski, and M. S. Beck, IEEE TransInstrum. Meas. 37, 3681988.4 J. T. Kung, H.-S. Lee, and R. T. Howe, IEEE J. Solid-State Circuits 23,972 1988.5 M. Yamada, T. Takebayashi, S. Notoyama, and K. Watanabe, IEEE TransInstrum. Meas. IM-41, 811992.6 H. Matsumoto and K. Watanabe, IEEE Trans Instrum. Meas. IM-35, 5551989.7 R. F. Wolffenbuttel and P. P. L. Regtien, IEEE Trans Instrum. Meas.IM-36, 868 1987.8 A. Ashrafi, M.Sc. thesis, K. N. Toosi University of Technology, Tehran,Iran, 1995 in Persian.9 J. Wong, Analog Devices, Application Note, AN-107 1987.10 H. Golnabi and A. Ashrafi, IEEE Trans Instrum. Meas. IM-45, 3121996.11 J. M. Jacob, Industrial Control Electronics Prentice-Hall, EnglewoodCliffs, NJ, 1989.12 M. L. Mead, J. Phys. E 15, 395 1982.13 W. Chr. Heerens, J. Phys. E 15, 137 1982.14 H. W. Ott, Noise Reduction Techniques in Electronic Systems Wiley,New York, 1988.15 P. Brokow, Analog Dialogue Analog Devices Inc. 11, 101977.16 J. C. Kuenen and G. C. M. Meijer, IEEE Trans Instrum. Meas. IM-45, 891996.