MPU-6000 and MPU-6050 Product Specification Revision 1.0

MPU-6000/MPU-6050 Product SpecificationDocument Number: PS-MPU-6000A-00Revision: 1.0Release Date: 11/24/20106.7 I 2 C Timing CharacterizationTypical Operating Circuit of Section 7.2, VDD = 2.5V±5%, 3.0V±5%, or 3.3V±5%, VLOGIC (MPU-6050 only)= 1.8V±5% or VDD, T A = 25°CParameters Conditions Min Typical Max Units NotesI 2 C TIMINGI 2 C FAST-MODEf SCL, SCL Clock Frequency 400 kHzt HD.STA, (Repeated) START Condition Hold0.6 µsTimet LOW, SCL Low Period 1.3 µst HIGH, SCL High Period 0.6 µst SU.STA, Repeated START Condition Setup0.6 µsTimet HD.DAT, SDA Data Hold Time 0 µst SU.DAT, SDA Data Setup Time 100 nst r, SDA and SCL Rise Time C b bus cap. from 10 to 400pF 20+0.1C b 300 nst f, SDA and SCL Fall Time C b bus cap. from 10 to 400pF 20+0.1C b 300 nst SU.STO, STOP Condition Setup Time 0.6 µst BUF, Bus Free Time Between STOP and1.3 µsSTART ConditionC b, Capacitive Load for each Bus Line < 400 pFt VD.DAT, Data Valid Time 0.9 µst VD.ACK, Data Valid Acknowledge Time 0.9 µsI 2 C Bus Timing DiagramCONFIDENTIAL & PROPRIETARY 16 of 53