Roadmap of SiGe BiCMOS Technologies - Avsusergroups.org
Roadmap of SiGe BiCMOS Technologies - Avsusergroups.org Roadmap of SiGe BiCMOS Technologies - Avsusergroups.org
- Page 3 and 4: Continued dominance of bipolar in R
- Page 6 and 7: Technology cost comparisonsRelative
- Page 8 and 9: Wireless: 3G System Block DiagramDi
- Page 10 and 11: Outline• Device Design for 200 GH
- Page 12 and 13: Device Design for 200 GHz Ft and Fm
- Page 14 and 15: SiGe Emitter Resistance1/Ft ~ (Re +
- Page 16 and 17: SiGe Base Width1/Ft ~ (Re + kT/Ic)
- Page 18 and 19: SiGe Base WidthPeak Ft (GHz)-25% Wb
- Page 20 and 21: SiGe BiCMOS Landscape (Dec ‘01)Ft
- Page 22 and 23: 0.18 µm SiGe BiCMOS Process Integr
- Page 24 and 25: SiGe BiCMOS: IsolationDeep TrenchJu
- Page 26 and 27: SiGe BiCMOS: Gate FormationGatePock
- Page 28 and 29: SiGe BiCMOS: CMOS / SilicideCo Sili
- Page 30: Conclusions• The bipolar device h
Continued dominance <strong>of</strong> bipolar in RFIC• BJT/HBT higher performance than MOSFET– MOS moving from MHz to GHz– BJT moving from 1-2 GHz to >200 GHz• Significantly lower cost than GaAs• High-level integration complexity with <strong>BiCMOS</strong> technology at moderate costpenalty
<strong>SiGe</strong> RF big bang250200Si<strong>SiGe</strong>BJT technology curve• Exceptional technologicalprogress in
Technology cost comparisonsRelative cost / unit area10.90.80.70.60.50.40.30.2<strong>SiGe</strong>CMOSTechnology node cost trends<strong>SiGe</strong> <strong>BiCMOS</strong>CMOS• Cost curves advance nearparallel• <strong>BiCMOS</strong> has moderate costpenalty over CMOS at sametechnology node0.10.5 0.4 0.3 0.2 0.1Technology Node
Performance-Cost comparisonsRelative cost / unit area - GHz0.020.010.0090.0080.0070.0060.0050.0040.003Normilised technology node cost for Ft GHz performanceCMOS<strong>SiGe</strong> <strong>BiCMOS</strong><strong>SiGe</strong>CMOS• Overall more performance atless cost• skewed curves withadvantage to <strong>BiCMOS</strong>beyond 0.10µm0.0020.5 0.4 0.3 0.2 0.1Technology Node
Wireless: 3G System Block DiagramDisplayBluetooth GPS3G Radio2.5G RadioWLANA/DBasebandProcessor(2.5G/3G)KeypadMicrophoneSpeakerCameraPower Amplifiers RF Subsystem BasebandGaAs or <strong>SiGe</strong><strong>SiGe</strong> <strong>BiCMOS</strong>CMOS
Wireline: Optical Networking Block DiagramSwitchFabricNetworkProcessorNetworkProcessorFramerForwardErrorCorrection(FEC)DemuxCDRMuxCMULimAmpReceiverTIA PINTransmitterDriver LaserOptical ModuleCMOS10 Gb: CMOS / <strong>SiGe</strong> <strong>BiCMOS</strong>40-80 Gb: <strong>SiGe</strong> <strong>BiCMOS</strong> / III-VIII-V
Outline• Device Design for 200 GHz Ft and Fmax• 0.18 µm <strong>SiGe</strong> <strong>BiCMOS</strong> Process Integration
Device optimization parameters• Aggressive vertical scaling to minimizediffusion component– Band-gap engineering– Collector doping– Emitter resistance (Re)– Base width reduction (Wb)• Aggressive lateral scaling to minimizedepletion terms– Emitter width (We)– SA emitterfTf1=2πτecmax=⎧ ⎡= ⎨2π⎢R⎩ ⎣e( C8je+ Cjc) +kTqIc( C + C )beDepletion termsfπ RbTCbcbc+ R CcbcW+ηD2bbWc+2vdiffusions⎤⎫⎥⎬⎦⎭−1
Device Design for 200 GHz Ft and Fmax250200(Re + kT/Ic) (Cbe + Cbc)Wb 2 / (2 Db)Measured Ft (Ghz)1501005000.1 1 10 100Ic (mA)
<strong>SiGe</strong> Collector Doping1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb 2 / (2 Db) + Wc/(2 Vs) + Rc Cbc200175150Peak Ft (GHz)1251007550250CalculatedMeasured0 1 2 3 4Normalized Collector Doping
<strong>SiGe</strong> Emitter Resistance1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb 2 / (2 Db) + Wc/(2 Vs) + Rc Cbc2250.5x RePeak Ft (GHz)20017515012510075502502x Re0 1 2 3 4Normalized Collector Doping
<strong>SiGe</strong> Emitter Resistance1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb 2 / (2 Db) + Wc/(2 Vs) + Rc Cbc250225Re=0Peak Ft (GHz)20017515012510075502502x Re0 1 2 3 4Normalized Collector Doping
<strong>SiGe</strong> Base Width1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb 2 / (2 Db) + Wc/(2 Vs) + Rc Cbc225200-12% WbCarbon DopingPeak Ft (GHz)175150125100755025+12% Wb+ Reduces B diffusionDegrades mobilityIncreases EgReduces Wb00 1 2 3 4Only small improvement in FtNormalized Collector Doping
Base narrowing for performance gain180Performance contribution from base narrowing160140FtLeap120Ft (GHz)1008060400.0 5.0x10 -6 1.0x10 -5 1.5x10 -5 2.0x10 -5 2.5x10 -5 3.0x10 -5W b -2 (Å -2 )
<strong>SiGe</strong> Base WidthPeak Ft (GHz)-25% Wb, Re=0350300250200150100+12% Wb5000 1 2 3 4Normalized Collector Doping
Lateral Scaling1/Ft ~ (Re + kT/Ic) (Cbe + Cbc) + Wb 2 / (2 Db) + Wc/(2 Vs) + Rc CbcFmax = ( Ft / (8π Rb Cbc) ) 1/2200180Ft (Ghz)160120800.15 µm0.30 µm0.20 µmFmax (Ghz)15012090600.30 µm0.20 µm0.15 µm403000.1 1 10 100Ic (mA)00.01 0.1 1 10 100Ic (mA)Good scaling properties maintain Ft constant as We is reduced increasing Fmax
<strong>SiGe</strong> <strong>BiCMOS</strong> Landscape (Dec ‘01)Ft (GHz)25020015010050Ft (GHz)2502001501005000.0 0.5 1.0 1.5 2.0 2.5Current Consumption* (mA)* Current required to reach peak Ft for minimum We and Le=1µm00 50 100 150 200Fmax (GHz)200 GHz Ft/Fmax opens the door to 80 Gb applications in Silicon
Outline• Device Design for 200 GHz Ft and Fmax• 0.18 µm <strong>SiGe</strong> <strong>BiCMOS</strong> Process Integration
0.18 µm <strong>SiGe</strong> <strong>BiCMOS</strong> Process IntegrationBase<strong>SiGe</strong> NPNEmitterCollectorNFET and PFETDrainGateSourceN+ Buried LayerPwellNwellDeep TrenchP- Substrate
<strong>SiGe</strong> <strong>BiCMOS</strong>: Buried Layer IntegrationEpi-Based1. N+ Buried Layer Implant2. Buried Layer Drive3. N- EpitaxyEpi-Less1. High energy N+ Buried Layer ImplantN+P-N-N+P-Lower Collector ResistanceLower CostLower Collector Substrate Capacitance
<strong>SiGe</strong> <strong>BiCMOS</strong>: IsolationDeep TrenchJunction1. Deep Trench Etch2. Deep Trench Oxide/Polysilicon Fill3. N/Pwell Formation• N/Pwell FormationN+P4x Lower Collector-Substrate CapacitanceLower Cost
<strong>SiGe</strong> <strong>BiCMOS</strong>: Collector ImplantsUsed to differentiate multiple NPNs on the same waferCollector ImplantsGate70Pocket/LDD0.35 µm <strong>SiGe</strong> <strong>BiCMOS</strong> ExampleImplant60BVceo=2.5VFt (GHz)5040302010BVceo=3.8VBVceo=6.0V01.E-05 1.E-04 1.E-03 1.E-02 1.E-01Ic (A)Trade<strong>of</strong>f between Ft, Cbc, and breakdown becomes a design variable
<strong>SiGe</strong> <strong>BiCMOS</strong>: Gate FormationGatePocket/LDDImplantGate formed prior to <strong>SiGe</strong> deposition to minimize thermal budget on NPN
<strong>SiGe</strong> <strong>BiCMOS</strong>: Emitter-Base IntegrationQSASelective EpiSacrificial EmitterExtrinsic Base Implant<strong>SiGe</strong>Extrinsic Base ImplantEmitter EdgeSpacer Separates EmitterFrom Extrinsic Base<strong>SiGe</strong>Selective <strong>SiGe</strong>+ Lowest Cost- High Rb+ Easy “Plug-in” to Si NPN+ Cjc self-aligned to emitter- Requires selective <strong>SiGe</strong>+ Lowest Rb+ Best Scaling Properties
<strong>SiGe</strong> <strong>BiCMOS</strong>: CMOS / SilicideCo SilicideCMOSSpacersS/DImplantsSRAM Cell• NPN films completely removed from CMOS regions• Silicide on all electrodes including emitter, base and collector
<strong>SiGe</strong>120 Cross-Section6 Layers <strong>of</strong> Metal 1.5 fF/µm2 MIM Capacitor3.0µm AlCu2µmW25 Ω/sq Metal Resistor1.5µm AlCuNPN Transistor
Conclusions• The bipolar device has continued dominance in RFIC space for theforeseeable future– <strong>SiGe</strong> has opened a permanent gap in performance vs. CMOS– <strong>SiGe</strong> <strong>BiCMOS</strong> Cost / Area / GHz is competitive with that <strong>of</strong> deep-subµ CMOS• Aggressive vertical and lateral scaling has so far enabled 200 Ft/Fmax– Advancement <strong>of</strong> vertical pr<strong>of</strong>ile largely responsible for gains– Further device / process optimization en route to 300Ghz