in PDF Format - Embedded-Control-Europe.com

Dear Readers,
Glenn Perry,
General Manager
Embedded Systems Division,
Mentor Graphics
VIEWPOINT
Disruptive technologies do not
occur very often and they can be
very hard to see coming. They are
always interesting – because they
result in real progress. Embedded
software technology tends to
evolve without sudden change.
The gradual increase in the use of
Linux fits that model, but a disruption
is on the way...
If we look back to the introduction
of the PC nearly 30 years ago,
programming them was quite
challenging. The DOS operating
system provided a minimal set of
services and the software developer
needed to construct a com-
plete framework to support their application. For example, the developers
of a word processing program would need to include drivers
for every printer imaginable; a spreadsheet program would need
its own vast set of printer drivers. This was inefficient and inconvenient
for both developers and users. The introduction of Windows
(or, at least, Windows 3.0) changed all that. Although we commonly
think of Windows as being a graphical user interface (which it is),
it is primarily an application framework–aplatformonwhichapplications
can be developed in order to share common services.
Nowadays, printers come with a Windows driver.
For the embedded developer, the state of Linux has some similarities
to those early DOS days. Although Linux provides drivers, networking
and a file system, there is significant work required to assemble
and configure the environment as a foundation for the target
device. Enter Google Android and keep the Windows analogy in
mind. Although there is a perception that Android is an operating
system for smart phones, that is really just one possible application.
Android is an application platform that accelerates the software development
for sophisticated embedded devices, while providing an
optimized environment for information access and exchange.
While Linux may not be optimal for every application, it excels when
the wide range of drivers and networking are a benefit and hard
real-time performance is not required. For high performance and
minimal impact on resources, a conventional RTOS is a better fit.
Increasingly, we notice many devices have a need for both. That is,
hard real-time performance for some aspects of the system and
expansive framework services for other.
The good news is that a multi-OS on multi-core hardware offers a
solution. A good example is an enterprise printer. True real-time
performance is required for paper handling, drums control and ink
management, and dedicating a suitable microcontroller, using an
RTOS, to these tasks makes sense. Another CPU, running Linux/Android
is well suited to handling networking, file storage and a
sophisticated user interface.
A well-designed system, with software optimally deployed across
processors, is real progress. Disruption is upon us.
3 September 2009
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CONTENTS
Viewpoint 3
Software Development
Designing fail-safe storage systems
for embedded applications 6
MCIF – a systematic approach to
software delivery excellence 8
Microcontrollers
Cortex-M3 software modifications for
ARM7TDMI programmers 12
ARM-based SoCs as alternatives to
embedded board solutions 16
Low-power microcontroller design
using the ARM Cortex-M0 core 18
16-bit microcontrollers with
new real-time event handling structure 21
Minimizing ownership cost for motor
applications by energy saving 24
Testing & Debugging
New approaches simplify testing and
debugging of complex MCUs 26
How to perform integration
testing of embedded software 29
Product News 31
Cover Photo
HCC-Embedded
September 2009 4
Designing fail-safe storage systems
for embedded applications PAGE 6
This article investigates the design of complete storage solutions
for embedded systems with particular reference to HDDs, SSDs,
SD and CF cards, and raw flash.
MCIF – a systematic approach to
software delivery excellence PAGE 8
Measured Capability Improvement
Framework (MCIF) was introduced
as a systematic approach to incrementally
improving software and
systems delivery capability. The
iterative approach, illustrated with
a real-life scenario, helps organisations
to stay always focussed on the
next step of improvement which is
clearly defined and measured.
Cortex-M3 software modifications for
ARM7TDMI programmers PAGE 12
This article explains some typical modifications that may be
required to port code from the ARM7TDMI processor to the
Cortex-M3 processor, in order to execute more efficiently on the
Cortex-M3 or exploit some of its advanced features.
Low-power microcontroller design
using the ARM Cortex-M0 core PAGE 18
This article discusses the low power characteristics of the ARM
Cortex-M0-based LPC1100 microcontroller series, and the system
design techniques that minimize the amount of energy consumed
from a power source.
Minimizing ownership cost for motor
applications by energy saving PAGE 24
This article reviews a new generation
of microcontrollers which
enable energy-efficient control of
brushless DC motors, permanent
magnet synchronous AC motors
and AC induction motors,
achieving major savings in
electricity costs.
New approaches simplify testing and
debugging of complex MCUs PAGE 26
The IEEE 1149.1 (JTAG) standard
no longer meets all the demands,
in terms of speed, pin-count and
robustness, for debugging and
testing modern microcontrollers
and complex SoCs. This article
describes new developments
which promise considerable
improvements for debugging, flash programming and system test.

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internationally. All other trademarks are the property of their respective owners.

SOFTWARE DEVELOPMENT
Designing fail-safe storage systems
for embedded applications
By Dave Hughes, HCC-Embedded
This article investigates the
design of complete storage
solutions for embedded systems
with particular reference
to HDDs, SSDs, SD and CF
cards, and raw flash.
■ In recent years it has become much easier to
store large amounts of data even on small embedded
systems, with help from the continuous
advances in flash storage that consistently challenge
Moore’s law. For many developers of embedded
systems the data they store and manipulate
are extremely valuable. It is a complex
task that requires much thought and innovationtodesignasysteminwhichdataarestored
so that they are never lost or damaged, and are
always maintained in a consistent state. HCC-
Embedded has spent significant time and effort
to analyze, design and test reliable file system
solutions for embedded devices. This article investigates
the design of complete storage solutions
with particular reference to HDDs, SSDs,
SD and CF cards, and raw flash.
A standard media storage system is shown in
figure 1. It is important to understand this layered
approach when aiming for a reliable system.
The reliability requirements reach from
the top layer to the bottom layer: The application
requires an adequate level of service from
the file system; the file system requires an adequate
level of service from the drivers; the drivers
require an adequate level of service from the
storage media. Without sufficient reliability in
any of the three levels, failure becomes an option.
And these levels of service need to be clearly
defined, because it clearly makes no sense to
claim that a file system is fail-safe if the storage
devices are unreliable. Each layer of the system
needs to understand what fail-safety is for that
layer and what it requires of other layers.
Let us start by defining the requirements that an
application developer requires for fail-safe
storage. First, we need to know precisely what
fail-safe means. At HCC-Embedded this boils
down to two main features. 1) Any time a file is
written to the system the action of closing or
flushing the file will atomically switch its state
from the previous consistent state to the new
consistent state. Effectively, this leaves the decision
as to what is consistent to the application
developer. 2) In the event of unexpected reset of
the system at any point while operating, when
the system restarts all elements of the file system
will be coherent and all files will be in their
pre-restart consistent state.
This point of consistency needs to be emphasized,
because in any file system you need to determine
when the new added data are valid, and
therefore it is time to update the related metadata.
All writes to the file system remain uncommitted
to the storage media until a close or
flush is issued to signal that the new state
should be made valid. In this way the developer
can determine what a consistent state for the
data is. This does not mean that the data are not
written to the target media; it does mean that
the meta-data of the file still refer to the previ-
September 2009 6
ously chosen consistent state until you decide
otherwise. It also means that if you seek back in
a file and overwrite something, then an original
copy must be maintained. This ensures that, in
case an unexpected event occurs, the original
state of the file is valid and consistent. This
rather straightforward description of fail-safety
is the essence of a real, workable approach to
building fail-safe file systems that are truly
reliable.
HCC-Embedded file systems are designed to
achieve the fail-safe requirements defined, but
only if the underlying drivers and physical
media meet certain requirements. 1) The driver
must write the data in the same sequence as
it is received. This rule enforces the proper sequence
even when there is a cache, because
there is no possibility that a sector will be written
when a previously written sector has not
been written. 2) In the event of a physical reset
or power loss, any sector of data must be either
written, or the old sector contents must remain
valid. There should be no intermediate state in
which the contents of a sector are effectively
random. The switch from the old state of a sector
to new state must be atomic. It is possible to
design systems with different requirements, but
they must be clearly described and understood
to ensure that the system will meet the fail-safe
design goal. These seemingly simple requirements
are not easy to achieve because of the

Figure 1. Logical structure of a standard
media storage system
design of storage devices. A stable power supply
and a clean reset of power are mandatory, particularly
when using systems incorporating
flash memory. It is essential to have a brown-out
detection that resets a flash card when power
drops below a specified level. Without power at
an acceptable level, reliable writing of data cannot
be guaranteed. Various types of problems
can occur. For example, a write may succeed
when a previous one failed or a write or erase
fails, thus creating bad blocks in the system. Several
available flash-based cards experience complete
and permanent failure if you slowly drop
the power to them while writing. Others include
internal brown-out detection to avoid this.
An obvious solution for most of these issues is
to provide reliable power to the device. This is
not necessarily as simple as at first appears. Data
on device behaviour during power failure is
often difficult to obtain from manufacturers. As
a result, the worst-case time required to store all
outstanding data may be difficult to ascertain.
For devices of some manufacturers, such data
are available, and thus it is possible to design to
the published specifications. But, although
there is a workable solution for these cases, the
choices become somewhat limited. Unreliable
power will undermine an otherwise fail-safe file
system. Very few manufacturers, with only a few
notable exceptions, state clearly the operating
■ HCC: Embedded USB stacks for
PIC32 MCUs
HCC-Embedded releases complete embedded
USB Device, Host and OTG stacks for the Microchip
PIC32 range of microcontrollers.
HCC has ported its entire line of embedded
USB Device, Host and OTG stacks to the
PIC32 range of microcontrollers. With its release
HCC now offers its
News ID 342
characteristics of the storage devices in terms
that are useful to a designer of a genuinely failsafe
system. HCC has applied rigorous tests to
many commercially available solid state memory
cards. The vast majority have been shown
to exhibit non-safe behaviour. Only a small
number of cards that are acceptable for use with
fail-safe file systems are classified.
Hard Disk Drives (HDDs) are uniquely difficult
devices to use in reliable systems. The primary
problem is that they all contain an integrated
data cache that is generally difficult to control.
If the cache were easy to control, doing so
would decimate the disk performance. For all of
the drives we have investigated, we have not
found one that will clearly state worst case scenarios
at power-off and how much time and
power are required to ensure that the contents
of the cache are safely written. If the safe flushing
of the cache cannot be guaranteed, then you
have worst case scenarios in which large
amounts of data are lost, and data that are
written later could be present.
SD cards, compact flash cards and solid state
drives all have similar design characteristics.
They contain arrays of NAND flash that are
managed by a flash translation layer (FTL),
which provides a logical sector interface to the
external system. The operation of FTLs is a
closely guarded secret by most manufacturers,
but it is clear that, to get maximum performance,
many devices employ caching and parallel
writing techniques. The result is that, in the
event of unexpected reset, sectors can be
written out of sequence.
Integrated flash has a major advantage: the
system design is then entirely under the developer
control. However, care must still be taken.
Looking again at the diagram if flash is to be interfaced
to the system then some kind of flash
management layer is required between the file
system and the flash. This is typically a flash
translation layer, which is incorporated into
SSD, SD card and compact flash card. It is imperative
that the FTL be designed to be fail-safe
and also that power is properly controlled. All
Product News
■ 'First Aid Kit - Edition 2' from EBV and TI
Based on Standard Linear and Logic ICs from
Texas Instruments, the EBV-TI 'First Aid Kit'
consists of a troubleshooting box containing a
description of various problems, the way to
solve them together with samples and
documentation to accelerate time-tosolution
implementation for R&D engineers
and technicians.
News ID 369
SOFTWARE DEVELOPMENT
media have their own peculiarities and weaknesses.
However, with proper understanding of
the medium behaviour, which can be very complex
and subtle, fail-safe systems can be built.
What are the primary conditions that can
cause a file system to be damaged? Firstly it is
useful to note that this can happen only when
a write or erase operation is being performed
on the target device. However, this could also be
the result of a user operation or of a management
function such as background erase or
wear-levelling. The two primary events which
can cause file system failure are: 1) unexpected
reset of the system because of power loss or
other hardware condition; 2) unexpected reset
of the system because of a bug. For example a
HDD typically contains a large internal cache (8
Mbytes or more), so if the disk loses power unexpectedly,
then the file system may lose data in
the cache, and much data could be written out
of sequence. A file system claiming fail-safety
really needs to specify what it can tolerate and
still remain failsafe, and then the design needs
to reflect that.
To ensure the failsafe characteristics of a file
system, and also to understand the issues that
arise, HCC has carried out extensive testing in
two main forms. 1) Simulation. The entire file
system and the drivers can be tested in simulation
on a PC. Millions of iterations of failure
scenarios can be generated very quickly and it
is possible to verify the design of the file system.
2) Test on an embedded system. Simulation of
course does not test the system with the target
media, and as illustrated it is crucially important
to ensure that it provides the quality of
service required. This is particularly true when
device manufacturers do not provide detailed
information about how their storage devices
operate. This testing is done by using an external
circuit to randomly reset the target. On each
reboot a verification program checks to see if
the contents of the system have been damaged.
Intensive testing of many SD cards has shown
that very few meet the requirements of atomicity
and sequential writing, and as such are not
suitable when data are important. ■
■ Ashling adds support for TI’s Code
Composer Studio 4
Ashling Microsystems has added support for
Version 4 of Texas Instruments Code Composer
Studio on its Opella-XDS560 Debug Probe.
Version 4 of Code Composer Studio is based on
the Eclipse open source software framework.
Opella-XDS560 is a high performance JTAG
Debug Probe targeting TI DSP Platforms.
News ID 423
7 September 2009

SOFTWARE DEVELOPMENT
MCIF – a systematic approach to
software delivery excellence
By Steven Trevellion, IBM Rational
Measured Capability
Improvement Framework
(MCIF) was introduced as
a systematic approach to
incrementally improving
software and systems delivery
capability. The iterative
approach, illustrated with
a real-life scenario, helps
organisations to stay always
focussed on the next step of
improvement which is clearly
defined and measured.
■ Nowadays business environment requires
development organisations to continuously
improve their capability to deliver high quality
systems and software. This is particularly true
for companies developing embedded systems
because factors such as innovation and agility
are key to building a competitive advantage, in
addition to the more familiar concerns of cost,
schedule and quality. In addressing all these factors,
both economic and engineering discipline
is required. Strategic risk-taking to explore new
opportunities and good decision-making must
rely on objective data to identify real business
value. The IBM Measured Capability Improvement
Framework (MCIF) provides a systematic
approach to incrementally improving software
and systems delivery capability. A capability
in this context means the combination of
process, tools, assets and skills that enable an organisation
to efficiently and effectively execute
an aspect of software development that results
in delivered software. Figure 1 provides an
overview of the capabilities addressed within
MCIF, grouped into three categories; business
focused, delivery focused and foundation.
Business-focused capabilities apply across one
or more projects and, as a result, are more closely
aligned with the business. Enterprise Architecture
is the ability to define all aspects of the
enterprise (such as e.g. business strategy, business
processes, information, infrastructure and
applications) as well as any transition planning
and governance. Product and Portfolio Management
is the ability to manage products
and/or product lines as a portfolio and thereby
increase the predictability of product development
and alignment to business strategy. Delivery-focused
capabilities apply to the execution
of a single software development project
that is focused on delivery: Project Management
is the ability to manage projects to agreed
parameters e.g. stakeholder management, planning,
staffing, executing, monitoring and risk
management. Requirements Definition and
Management is the ability to define, validate
and manage requirements resulting in improved
collaboration and communication
among business stakeholders and project teams.
Analysis and Design contains the ability to
transform all requirements into a solution
that has a robust architecture and sufficient
design to govern and guide construction.
Construction is the ability to perform detailed
design tasks, source code organisation, to
implement, unit test and integrate the code into
an executable system ready for system verification
and quality testing. Quality Management
is the ability to ensure the required level of
quality exists in the products or systems. Release
Management is the ability to repeatedly and
reliably build an auditable release of products or
systems.
September 2009 8
Figure 1. Software delivery
capabilities
Foundation capabilities apply to all other capabilities
and are in general a prerequisite for
other capabilities. For example, quality management
is of limited use unless the associated
work products are managed within a configuration
and change management capability i.e.
the system under test is of a known, reproducible
state. Lifecycle Processes contain the
ability to follow a defined process (or method).
Configuration and Change Management is
the ability to uniquely identify and control all
elements of a system that are required to be
under configuration control and control
changes to work products including version
tracking and audit histories. Asset Discovery,
Management and Re-use is the ability to identify,
create, maintain and retire re-useable assets
in such a fashion as to facilitate easy discovery
and re-use on subsequent products / systems.
Figure 2. Value traceability tree

Measurement and Reporting includes the ability
to provide measurements and reports (based on
meaningful metrics) aligned with business value
to inform business and development related
decision making. There are inter-relationships
between capabilities which can be as important as
the capabilities themselves. As an example, the
traceability from requirements to design and test
elements provides the ability to perform an impact
analysis of any proposed changes. The MCIF
approach to instantiating or improving these
capabilities is to follow a four phase approach:
■ In the Target phase, business stakeholders define
the set of business objectives (such as rapidly
responding to market opportunities) before
they work with development specialists to determine
the associated engineering objectives
(such as reducing product development times).
The objectives are prioritised and over-arching
strategies to achieve these objectives are defined.
Each business and engineering objective has
success criteria agreed to create a common view
ofhowwewillknowwhenwehavesucceeded.
■ In the Map phase, engineering objectives are
mapped to delivery capabilities within the development
organisation. Dependencies between
capabilities and other interdependencies are
identified and the deployment of capabilities
time ordered resulting in a roadmap that provides
a clear picture of when the engineering objectives
(and, therefore, the business objectives
that they are derived from) will be achieved.
■ In the Adopt phase, the roadmap is executed.
Capabilities are deployed via pilot and roll-out
projects. Self-checking by the development
teams enables monitoring and steerage of the
adoption within an adoption cycle.
■ In the Review phase, progress towards the
business objectives is reviewed and any corrections
in the approach applied. Focus then typically
returns to the next adoption phase to address
the next increment of capability deployment.
On occasion, earlier phases may be revisited
if significant refactoring is required due
to market or business changes.
The following example illustrates how the
MCIF approach helped a mobile telecommunication
company. The actual case is fictitious
but is based on real-world scenarios and experience
gained by IBM Rational Software assisting
customers to improve their software delivery
capability over the last 20 years. The company,
although successful to date, knows that it
needs to undertake significant change to continue
as a market leader. Software and systems
engineering disciplines are well established
and mature, but are struggling to respond to
imprecise or fuzzy demands in a highly-charged
and dynamic marketplace. The company
Figure 3. Self check results
SOFTWARE DEVELOPMENT
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SOFTWARE DEVELOPMENT
Figure 4. Trend of risk retirement
decides to undertake an improvement programme
based on a systematic, measurable
approach (MCIF). The lines of business, product
marketing and the development organisation
conduct a business value workshop (part
of MCIF phase 1). This determines the key
business objectives and the measures that will
be used to inform steering. These are identified
as: increase ability to be first in the market with
innovative features (percentage of market leading
products), meet market opportunity windows
(products must meet production deadlines
to hit seasonal market release campaigns,
percentage of product campaigns launched
on time), and maintain reputation for quality
products (number of customer complaints,
number of returned products). Note that these
are in addition to the existing revenue, profit
and market share measures the company uses
to govern and manage the business.
The engineering objectives required to support
the business objectives are defined: improve
business alignment; engineering must be “intune”
in terms of collaborating with product
marketing on new product features and
requirements (average percentage of product
requirements agreed between stakeholders); increase
product innovation, engineering must
use its expertise to invent ways of harnessing
new technology resulting in new features and
market opportunities (number of new innovations
per quarter year); reduce product development
time, engineering must make efficiency
gains in order to deliver products in
shorter timescales (average project schedule),
reduce project schedule uncertainty; engineering
must increase its ability to deliver product
commitments on schedule (project schedule
variance), and maintain product quality and reliability;
engineering must continue to uphold
development rigour in terms of product quality
and reliability (escaping defect rate, mean
time between failures, MTBF).
The over-arching strategy selected is to adopt an
iterative, risk-driven development process in
which engineering rigour is right-sized to
provide the optimum balance between gover-
Figure 5. Trend of the number of checked-out
work items
nance and change stability needed to enable
flexibility to respond rapidly to changing
market conditions and to get innovations into
production. In phase 2 the strategy is used to
steer the selection of capabilities required to
meet the agreed objectives. A high-level view of
the resultant mapping (value traceability tree)
of business objectives to engineering objectives
to capabilities is provided in figure 2. In parallel
the measurement system is developed to define
the metrics to be used to monitor the
improvement programme. A summary of the
engineering capabilities and associated metrics
is given below:
Requirements Management: The shared vision
replaces the existing manual feature and requirement
registers with a shared environment
where all stakeholders have easy access to definitions
and status. Associated metrics: No
measure – this is effectively monitored as a binary
function (Stakeholders do/do not have access
to shared view) – the impact being evident
in the requirement trend metrics given below.
The story-board elicitation augments the existing
textual requirements definitions with
story-boarding and other elicitation techniques
to aid collaboration and common understanding
of imprecise needs. Associated metrics:
Trend of requirements outlined, specified,
agreed. In the Project Management Iterative development
the development project is broken
down into a series of successive iterations. Each
iteration has a fixed plan (budget and schedule)
including allocated requirements, development
activities and resources, results in a verified,
demonstrable system of incremental functionality,
and has a change gate permitting requirement
changes in the early, requirementsfocussed
part of the iteration (circa 20% of the
schedule), then closing to provide iteration stability.
Associated metrics are: Iteration burndown
(percentage complete, remaining estimate),
Schedule Performance Index (SPI),
Cost Performance Index (CPI), percentage iteration
stable (percentage change gate open,
closed). In the Risk-value lifecycle the content
of iterations is prioritised by risk (to drive risk
www.embedded-control-europe-com
September 2009 10
Figure 6. Trend of test time (hours per system
test)
resolution as early as possible in the lifecycle)
and business value (to deliver more valuable
content first). Prioritisation is reviewed at the
end of each iteration based on results and planning
for subsequent iterations adjusted as required
(the overall programme is steered to the
optimum outcome for all stakeholders). Associated
metrics are trend of risks retired (H, M,
L magnitude), trend of value implemented.
The Configuration and Change Management
includes formal management and automation.
Formal change management is the formal
process to uniquely identify and control all development
elements of the system (requirements,
design, implementation source code) including
version tracking and audit histories. Associated
metrics are the trend of the number of
work items configured (check in/out), trend of
the number of change requests/status. Automation
contains tooling support for configuration
and change management workflows.
Provides a fully configured developer workspace
and functionality to draw down (or be
dynamically updated) a complete set of configured
(or latest) work items from across the
development team (local and remote). Associated
metrics are the percentage effort spent on
CCM activities. The Quality Management includes
continuous verification which means
complete system testing (functional and performance),
informal during iterations and formal
for the end of iteration product. Associates
metrics are the trend of number of defects
(open, closed), mean time between failures
(MTBF). Its Automation contains tooling support
for automated functional and performance
testing including reporting and generation of
change requests based on identified defects.
Associated metrics includes the trend of test
time per build.
With the capabilities and their associated
metrics defined the next step is to define the
roadmap, the high-level plan for adoption. Dependencies
between capabilities are identified,
the capabilities time ordered and a roadmap for
a pilot project created. Five capabilities are

instantiated in part I, the reasoning is provided
by shared vision: provides the shared view of
requirements across the stakeholder community
that supports the new requirement elicitation
techniques of the story-board elicitation
capability; formal change management and associated
automation provide the mechanism
for control of configuration and change required
by iterative development and the allocation
and management of iteration content
(risk-value lifecycle), and continuous verification
and associated automation provide the
mechanism for informal and formal system
functional and performance testing required for
the verification of risk removal and value
earned during each iteration.
Aliveprojectwasselectedtopilotadoptionof
the new capabilities (MCIF Phase 3). The selection
of a live project ensured that the pilot attracted
a high level of stakeholder visibility and
that the outcome (positive or negative) reflected
results in a true business context. At the end
of the pilot, after six months, a formal business
review was conducted. As the results were
judged a success and no major refactoring was
required the adoption moved on to propagate
the improvements made across the organisation
via a number of waves. Each wave addressed
one or more projects within the organisation:
Wave 1, three further live projects of approximate
duration 6 months, Wave 2, all new projects,
and Wave 3, selected legacy systems. As
each capability comprised a package of process
elements, tooling support, assets and staff enablement,
a central team was setup to manage
the provision of each of these elements to project
teams starting adoption. Enablement was
provided via quick-start workshops and on
project mentoring. Process, assets and supporting
tooling were provided as an integrated,
collaborative development environment
configured to meet the needs of each project.
A self-check tool was used by the teams undertaking
the projects to ascertain their adoption
progress. The example in figure 3 shows
the results of one of the project teams in wave
1 self-checking their adoption of the new project
management capabilities. The team scored
the adoption as high for iteration planning, risk
allocation and value allocation to iterations but
low for successive demonstrable systems. In
practice this meant the iterations were not resulting
in executable, verifiable systems (of incrementally
increasing functionality). This was
a serious error in the adoption as demonstrable
systems are required for the valid retirement of
risks, value based progress reporting and steering.
A short period of intensive mentoring was
undertaken to re-plan subsequent iterations
and train the project teams. Subsequent self
checks showed that the capability to deliver
successive demonstrable systems was in place.
SOFTWARE DEVELOPMENT
Having reached a major adoption milestone
(end of pilot project) a steering board was convened
(MCIF Phase 4 Review). Figure 4 provide
three examples of the capability level results reviewed.
This chart shows the retirement trends
for risks classified as high and medium magnitude.
In the risk-value lifecycle retirement of a
risk means that there is demonstrable evidence
that the risk has been mitigated. For example,
in iteration 1 testing proved that the system
under development had met critical technical
performance requirements identified as high
magnitude risks and therefore those risks were
retired. By the end of iteration 2 the pilot
project had retired all high magnitude risks.
Figure 5 shows the trend of the configuration
state of work items (checked in/out) across the
pilot project iterations. The trend shows the efforts
made by the team to put work items under
configuration control (checked-in) ready for
formal system testing at the end of each iteration
(the dips towards zero items checked-out
at the end of iterations). By the end of the final
iteration the project had achieved 100% of
work items under full configuration and change
control.
Figure 6 tracks the time the pilot project spent
per system test. At the start of the project the
initial testing took approximately four days of
effort. This was consistent with historical data
for manually intensive testing on previous
projects. As the testing was automated and
experience of the new testing environment
improved this time was reduced to approximately
six hours. The review board judged the
results as significant improvements. By referring
to the value traceability tree they were able to
see the linkage from these results to the engineering
objectives and therefore the business
objectives.
The board approved continuation of the programme
to wave 1, adoption on three further
six month duration projects (returned to MCIF
phase 3 for next adoption cycle). Wave 1 delivered
the expected results across two of the three
projects selected. The project that did not deliver
the same level of results was examined. The
issue was identified (as described in the example
self-check results) and corrective action
taken but the time lost was not fully recovered.
The cause of the issue was identified as insufficient
skills enablement of the project team and
the resources within the central support team
were increased to prevent re-occurrence. Today,
the improved capabilities are adopted as business
as usual for all new projects launched. The
board is now considering the application of
capabilities to selected legacy systems and the
options for further capability improvement in
the areas of asset re-use and product and
portfolio management. ■
11 September 2009

MICROCONTROLLERS
Cortex-M3 software modifications for
ARM7TDMI programmers
By Joseph Yiu and Andrew Frame, ARM
This article explains some
typical modifications that may
be required to port code from
the ARM7TDMI processor to
the Cortex-M3 processor, in
order to execute more
efficiently on the Cortex-M3
or exploit some of its
advanced features.
■ The Cortex-M3 processor, introduced in
2006, has some innovative and much improved
features and capabilities when compared
with the ARM7TDMI processor. The
richer instruction set and improved efficiency
of the Cortex-M3 Thumb instruction set architecture
(ISA) technology enables better optimized
program code to be generated, alongside
other code-saving advantages. Since the
Cortex-M3 processor can finish a task quicker
than an ARM7TDMI, more time can be spent
in sleep mode, reducing the active power of the
system and thereby enabling better system
performance and energy efficiency. Alternatively
the higher performance can be used to
implement more advanced application features.
A number of bit field manipulation instructions
are supported by the Cortex-M3 processor
that can improve the performance and code
size when dealing with bit fields, for example, in
peripheral controls and communication protocol
processing. The Cortex-M3 processor
supports two bit band memory regions, one for
SRAM and one for peripherals. The use of bit
band memory accesses can simplify peripheral
control processes, and can reduce SRAM
usage by converting Boolean variables into bit
band alias accesses with each Boolean data taking
only one bit. The nested vectored interrupt
controller (NVIC) in the Cortex-M3 processor
is easy to use, and provides flexible interrupt
control with much simpler interrupt handling
code along with the added benefit of priority
level control to give better interrupt handling
performance. The fast single-cycle multiply and
new hardware divide instructions can enable
further optimized ARM7TDMI processor assembly
data processing routines for DSP and
saturate-like functionality. A number of low
power sleep modes have been introduced in the
Cortex-M3 processor which are not available in
the ARM7TDMI processor. Entering low power
mode is done by executing wait for interrupt or
wait for event (WFI/WFE) instructions. If the
optional MPU is implemented then it can be
used to improve the robustness of the application
and accelerate the detection of errors
during the application development.
The ITM module in the Cortex-M3 processor
can be used to provide diagnosis (or debug)
messages through the serial wire viewer (SWV)
using standard debug hardware. For example, a
retargeted function fputc can be implemented
to write to the ITM stimulus port registers so
that when the printf function is executed, the
message is output to the serial wire viewer connection,
captured by the debug hardware and
subsequently displayed in the ITM viewer window.
The processor provides a number of special
instructions to increase the performance in
September 2009 12
data processing, for example, bit field insert, saturation
and endian conversion for data. Some
of these instructions can be generated by the C
compiler using idiom recognitions or intrinsic
functions.
The modifications required to enable
ARM7TDMI processor software to run on a
Cortex-M3 processor will depend on the complexity
of the ARM7TDMI software and how it
was written. The remainder of this article is divided
into different sections, based on the
type of software that needs to be ported. Table
1 shows a brief outline of the modification scenarios
for porting code from the ARM7TDMI
processor to the Cortex-M3 processor.
It is recommended that all C code be recompiled
so that it can be optimized for the more
powerful Cortex-M3 Thumb instruction set,
and also to ensure that all obsolete state switching
code (between ARM and Thumb states) is
removed. The ARM7TDMI processor supports
both ARM and Thumb code, and although
Thumb code compiled for ARM7TDMI
will work, the Cortex-M3 instruction set should
enable higher levels of performance whilst
maintaining the industry-leading code density
offered by the original ARM7TDMI Thumb instruction
set. If the C code is purely ANSI C
then no further changes will be required. Non-

Software type Modifications
Part A: Simple applications
written mostly in C
Part B: Applications with mixed
C and assembly code.
Part C: Complex application with
embedded OS, 3 rd party software
libraries.
Table 1. Brief outline of the modification scenarios for porting code from the ARM7TDMI
processor to the Cortex-M3 processor
ANSI C code functions, for example, state
changing pragma directives (#pragma arm
and #pragma thumb), which are required to
support the two different ARM7TDMI
instruction sets, no longer apply and must be
removed. The Cortex-M3 processor requires an
extremely simple start-up sequence which can,
if desired, be written completely in C. This
C code should be recompiled for the Cortex-M3 to take
advantage of the more powerful instruction set with only
minor modifications being needed.
Startup code (including the vector table) needs to be
simplified.
Interrupt controller setup code needs to be updated to
take advantage of the integrated interrupt controller
hardware and the removal of the need to provide top level
interrupt handler code.
Interrupt handler wrapper code needs to be simplified.
Sleep mode entry code may need to be added to
implement the Cortex-M3 architected low power modes
for reducing power consumption.
Stack memory layout may need to be considered due to
the reduction in number of stacks that need to be
supported.
All modifications for Part A, plus a possibility of the need
to:
Change any assembler instructions to support Thumb-2.
Replace Software Interrupt (SWI) with Supervisor Call
(SVC), and update SWI (SVC) handler.
Adding or adjusting fault handlers.
All modifications for Parts A and B, plus :
Changing of embedded OS and 3 rd party libraries to
updated versions for Cortex-M3.
Differences ARM7TDMI Cortex�M3
Modes Seven modes : Supervisor,
System, User, FIQ, IRQ, Abort,
Undefined
Program Status
Registers
Current Program Status Register
(CPSR), and banked Saved
Program Status Register (SPSR)
Two modes: Handler mode and Thread
mode. Thread mode can be privileged or
non privileged.
xPSR : containing Application, Interrupt
and Execution Program Status Registers
(APSR, IPSR, and EPSR). The I and F mode
bits are removed. The SPSR is removed
because xPSR is saved onto the stack
during exception entry.
Stack Up to six stack regions Up to two stack regions
States ARM state and Thumb state Thumb state only
MICROCONTROLLERS
Table 2. Brief outline of differences in programmers models between the ARM7TDMI processor
and the Cortex-M3 processor
start-up sequence consists of a vector table with
an initial value for the main stack pointer
(MSP) followed by a vector address for each exception,
with the possibility to enter main or C
initialization code directly from the reset vector,
or via optional start-up code. While microcontrollers
based on the ARM7TDMI processor
would generally have a separate interrupt
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MICROCONTROLLERS
Addressing modes Supported in ARM7TDMI Supported in Cortex-M3
Increment after – address
increment after each access
Increment before – address
increment before each access
Decrement after – address
decrement after each access
Decrement before – address
decrement before each access
controller, the Cortex-M3 processor contains an
integrated nested vectored interrupt controller
(NVIC). Since the address location and the
programmer model for the interrupt controllers
are likely to be different, the setup code
for the interrupt controllers would likely be
different. The use of an assembly code wrapper,
which is normally required with the
ARM7TDMI processor, can be completely
eliminated on the Cortex-M3 processor because
the exception mechanism automatically handles
nested interrupts, executes the correct
interrupt handler and handles saving and
restoring of a number of registers so that the
exception handlers can be programmed as C
functions.
It is possible that a program might behave
differently after being ported from
ARM7TDMI processor to the Cortex-M3
processor due to differences in execution speed.
For example, a system that uses software to generate
bit-bang operations like SPI and I²C
might achieve higher speeds when running on
a Cortex-M3 processor based microcontroller
and, as a result, it may be necessary to adjust
any software timing constant for the application
firmware. The Cortex-M3 processor has only
two stack pointers, and unless the software requires
an embedded OS or requires the separation
of privileged and non-privileged levels,
it is possible to use just one stack region for the
whole application. This makes stack memory
planning much easier and often results in the
stack memory size requirement on the Cortex-
M3 processor being much less. The initialization
of the second stack pointer (PSP – process
LDMIA/STMIA, POP (LDMIA /
LDMFD with SP as base)
LDMIB/STMIB -
LDMDA/STMDA -
LDMDB/STMDB, PUSH
(STMDB / STMFD with SP as
base)
Table 3. Load and store multiple address modes supported by the Cortex-M3 processor
Instruction ARM code Thumb (16-bit) Thumb (32-bit)
B label +/- 32MB +/-2K +/-16MB
stack pointer) can be performed by the start-up
code or by the OS initialization sequence.
Projects with mixed C and assembler code may
require additional modifications due to differences
in the model and instruction set of the
programmer. Whilst the ARM7TDMI and Cortex-M3
register bank (R0 to R15) registers are
similar, there are a number of modifications required
due to the simplification of the Cortex-
M3 programmer’s model. Table 2 lists the key
differences in the programmer models. The
Cortex-M3 programmer model is much simpler
than the ARM7TDMI because the handler
mode manages all types of exception in the
same way. Also, fewer banked registers results in
less initialization before entering the main
application. In most simple applications, only
a simple vector table is required and then the
rest of the coding can be done in C. The Cortex-M3
processor does not require state changing
branch veneers which switch the processor
between ARM and Thumb states and so any
state changing code in assembler files should be
removed.
All Thumb instructions on the ARM7TDMI
can execute on the Cortex-M3 processor. However,
the legacy SWI (software interrupt) instruction
has been renamed to SVC (supervisor
call), and its associated handler will require
modification (See SWI and SVC section). For
ARM assembler files, some care is needed to
avoid the few ARM instructions that do not
have a Thumb equivalent and cannot be used
on the Cortex-M3 processor. These are: Swap
(SWP) and Swap Byte (SWPB) instructions. In
the Cortex-M3 processor swap has been re-
September 2009 14
LDMIA/STMIA, POP (LDMIA
with SP as base)
LDMDB/STMDB, PUSH
(STMDB with SP as base)
BL label +/- 32MB NA – always 32-bit +/-16MB (was 4MB in ARM7TDMI)
B label
(Conditional branch)
+/- 32MB -252 to +258 +/-1MB, or
Table 4. Listing of the branch ranges for ARM and Thumb code
+/-16MB when branch instruction
is used with IT instruction block
placed by load and store exclusive access instructions
(LDREX and STREX). Load/Store
instructions. The Cortex-M3 processor supports
commonly used load and store multiple
address modes. Table 3 shows the load and store
multiple address modes supported by the Cortex-M3
processor. If the software code to be
ported was written for memory address arithmetic
using ARM instructions, the memory offset
value will need to be changed because the
value of PC would be the address of the current
instruction plus 4. The Cortex-M3 processor
conditional execution feature is supported by
placing instructions into an IT (If-Then) instruction
block with each IT instruction block
having up to 4 conditional instructions. With
the ARM development tools, the assembler automatically
inserts IT instructions into the
output image resulting in a simple software
porting process whilst maintaining very efficient
code density. Both the ARM7TDMI
processor and the Cortex-M3 processor support
move to register from status (MRS) and
move to status register (MSR) instructions but
the effects of these instructions differ in execution
on each processor.
On the Cortex-M3 processor, the interrupt
enable and disable is handled by a separate
exception mask register called PRIMASK and
the exception model has priority levels assigned
to each interrupt. Change processor state (CPS)
instructions allow the interrupt enabling or disabling
operation to be done in just one instruction.
The Cortex-M3 processor interrupt
enable/disable (PRIMASK) is separated from
the PSR so the restoration of PSR status at interrupt
returns does not change the interrupt
enable/disable behaviour. If the ARM7TDMI
application assumed that the interrupt would
be disabled when entering an exception handler,
and relies on this behavior, then the exception
handler must also be changed. The ARM instruction
“MOVS PC, LR” is used in
ARM7TDMI processor as exception return.
This must be changed to “BX LR” on the Cortex-M3
processor because the move instruction
(MOV) is not a valid instruction for exception
return.
When porting assembler code from ARM code
to Cortex-M3 Thumb code, some of the branch
and conditional branch instructions will need
modification to specify that the larger ranged
32-bit version of the instruction is used. This is
done by adding the .W suffix. For example,
BEQ.W label, table 4 lists the branch ranges for
ARM and Thumb code. The SWI instruction in
the ARM7TDMI processor equates to the SVC
instruction in the Cortex-M3 processor. The
binary encoding of the instruction remains
unchanged, but the handler code needs modification
if it needs to extract the immediate
value from the SVC/SWI instruction. ■

■ STM: STM32 MCUs with Ethernet, USB
OTG and CAN
STMicroelectronics confirms full production
availability of its latest STM32 Connectivity
Line microcontrollers built on the ARM Cortex-M3
processor. The STM32 Connectivity
Line allows developers to take advantage of industry-standard
32-bit processing in designs requiring
simultaneous Ethernet, USB, CAN
and audio-class I2S capabilities. Two variants
are available, including the STM32F105 series
combining a Full-Speed USB 2.0 Host/Device/OTG
peripheral and two CAN2.0B controllers
with advanced filtering capabilities.
News ID 1531
■ TI: system-on-chip metering solution
Supporting three-phase e-metering applications,
Texas Instruments announces the new
ultra-low power MSP430F471xx microcontroller
series. The F471xx system-on-chip metering
solution achieves leading accuracy results,
and offers simultaneous sampling of
voltage and current as well as tamper-detection
for efficient and reliable energy measurement.
News ID 1581
■ Microchip: PIC MCUs feature enhanced
mid-range 8-bit core
Microchip announces the first six members of
the PIC16F193X family of microcontrollers,
featuring Microchip’s enhanced mid-range 8bit
core. The increased memory and core capabilities
deliver enhanced support for both C
and Assembly programmers, while the ‘LF’ family
members feature Microchip’s nanoWatt
XLP Technology for extreme low power operation.
News ID 1898
■ Evatronix: 8051 MCU now fully supported
by ARM Keil Vision4 IDE
Evatronix announces full support of its
R8051XC2 microcontroller IP by the ARM Keil
Vision4 Integrated Development Environment.
μVision4 has been designed to enhance
developer’s productivity, enabling faster, more
efficient program development and verification.
The flexible window management system introduced
in Vision4 enables developers to use
multiple monitors and provides complete control
over window placement anywhere on the
visual surface.
News ID 1973
■ Digi-Key: community for Freescale
Tower System
Freescale Semiconductor’s new Tower System
and Towergeeks.org, is an online community
created for engineers by Digi-Key. The Tower
Product News
System is a modular, reconfigurable development
platform for 8-, 16-, and 32-bit microcontrollers
that allows designers to get to market
faster with packaged evaluation boards,
tools, and runtime software. Comprised of
three types of modules (microcontroller, peripheral,
and elevator modules), the Tower System
enables engineers to reuse tools and rapidly
prototype designs.
News ID 1614
■ Atmel: AVR MCU family with CAN and
LIN connectivity
Atmel announces a new family of AVR microcontrollers
targeted at the industrial control
market. The ATmega16M1, ATmega32M1, and
ATmega64M1 have been developed to serve the
need for high accuracy pulse width modulation
for advanced motor control applications with
CAN and LIN connectivity. The new family of
devices feature 16, 32, and 64 KB of Flash, general
purpose IO pins, analog to digital converter,
analog comparators, Power Stage Controller,
and 8 and 16 bit timers.
News ID 308
■ MSC: 6-pin tinyAVR features ultra-small
package
MSC announces ATtiny10, a new 6-pin tinyAVR
microcontroller from Atmel. As smallest device
in the growing tinyAVR family, it comes in a 6pin
SOT-23 package, measuring only 2.9 x 1.6
mm. The device fits in a wide range of applications
where size and cost are of high importance.
ATtiny10, with pin compatibility to Microchip’s
PIC10F products, features 16-bit timer/counter,
PWM outputs, combination of 8-bit ADC and
analog comparator, additional SRAM or the AVR
CPU for higher performance.
News ID 1502
■ Atlantik: ZigBee SoCs based on ARM
Cortex-M3
Atlantik Elektronik presents the new EM 300
series first ZigBee SoCs based on the 32-bit
ARM-Cortex-M3-processor. The EM300 Series,
the next generation ZigBee chip family that
packs the industry´s highest wireless networking
performance and application code space
into the lowest power-consuming chip set to
build sophisticated products for smart energy
and home area networks as well as home and
building automation.
News ID 1572
■ Renesas: SuperH solution for GUI
and video display applications
Renesas announces the latest members of its
SuperH line-up, built around the SH-2A core
with its superb realtime processing capability.
MICROCONTROLLERS
The SH7264 and SH7262 have been designed
for visualisation and GUI applications and offer
up to 1MB of on-chip SRAM. This allows video
display capabilities to be implemented without
the need for external RAM, thereby offering significant
reductions in overall system costs and
power consumption.
News ID 345
■ Beck IPC: 32-bit version of IPC@CHIP
controller
With the new IPC@CHIP SC2x3 Beck IPC
moved forwards to the field of 32-bitcontroller.
The IPC@CHIP SC2x3 represents
the consistent upgrading of the IPC@CHIP serial
for the area of high-end control applications
or fast data transmittal. Equipped with
760 MIPS at 400 MHz clock rate, 32 bits and integrated
double precision floating point unit,
the latest SC2x3-modules are predestined for
demanding tasks in the area of control and
communication.
News ID 1590
■ CML: 32-bit MCU for industrial sensing
and control
CML Microsystems has unveiled a new
RISC/DSP microcontroller product from its
specialist semiconductor and microprocessor
daughter-company, Hyperstone. The new E2 is
a high-performance, RoHS compliant 32-Bit
RISC/DSP microcontroller, with advanced features
such as a programmable serial communications
engine, ADC unit, 32kb of on-chip I-
RAM, complemented with an external memory
and peripheral interface controller.
News ID 1538
■ AMD: dual-core processors for
embedded platform
AMD announces availability of two new dualcore,
18W TDP processors for the highly-scalable
ASB1 BGA embedded client platform. The
AMD Turion Neo X2 processor Model L625
and the AMD Athlon Neo X2 processor Model
L325 deliver PC-caliber performance in a very
low power envelope and with an embeddedfriendly
ball grid array package.
News ID 302
■ Cyan: new 16-bit microcontroller
achieves 0.71 DMIPS/MHz
Cyan announces the launch of the eCOG16E01.
With Cyan’s new CyCore CPU at its heart, this
16-bit microcontroller outperforms other 16bit
MCUs. In Dhrystone v2.1 benchmarks, the
eCOG16E01 has achieved 0.71 DMIPS/MHz,
which exceeds the performance achieved by
leading MCU suppliers.
News ID 1484
15 September 2009

MICROCONTROLLERS
ARM-based SoCs as alternatives to
embedded board solutions
By Ruediger Senghaas, MSC-Gleichmann
Thanks to their high
computing power, multimedia
characteristics, and availability
of board-support packages,
e.g. for Windows or Linux,
SoCs such as the S3C6410
from Samsung present serious
competition to SoCs based on
Intel Atom processors, at least
in cost-sensitive systems.
■ What do mobile and stationary systems have
in common with TFT displays, media players,
telephone and radio equipment, industrial
controls and signal processing systems? They all
require a relatively high performance and
should preferably cost nothing. Of course,
ARM-based SoCs are not given away for free,
but at least you usually get an amazing amount
of performance for a comparatively small
amount of money. The following example of
the Samsung S3C6410X will show this. The
proven Harvard architecture serves as a basis for
ARM11 controllers. This enables simultaneous
access to program code and data whereby access
to the program code takes place via the 16
Kbyte instruction cache and also the 16 Kbyte
instruction TCM. Since the caches are dynamically
managed from the controller, the instruction
TCM helps with the processing of instructions,
which must be handled deterministically.
This includes, for example, interrupts.
The provision of the data takes place via the 16
Kbyte data cache and the equally-sized data
TCM. The latter can contain data in blocks that
require elaborate processing, e.g. audio or
video data. Both with the data TCM and the instruction
TCM, data from other memory areas
is made available via DMA.
Connection between the ARM1178JZF-S CPU
core and peripherals and respective memories
takes place via the level 2 interface. Data is sent
and received in compliance with the AMBA
AXI protocol. AMBA, an ARM-developed IP, is
an acronym for advanced microcontroller bus
architecture. Four interface protocols are specified
in the AMBA 3 specification: AHB (advanced
high-performance bus), APB (advanced
peripheral bus), ATB (advanced trace bus)
and AXI (advanced eXtensible interface). The
advanced eXtensible interface ensures the supply
of the caches with new data via 64-bit bandwidth
and is an essential element for increasing
the performance of the ARM architecture. It is
based on a master-slave concept. Since several
masters can be active on the bus, the access is
coordinated by a bus arbiter. Address and control
information between master and slave are
exchanged before the actual data transfer via
AXI. Therefore, in addition to providing the
destination address, information about data
length, transfer size and transmission characteristics
(burst modes, caching or buffering control,
atomic access, etc.) are also provided.
AXI also enables out-of-order transaction completion.
It this case, it concerns a process in
which each individual transaction that takes
place via the interface is furnished with an ID
tag. This enables sending and receiving of
data, without adherence to the correct sequence.
As a result, for example, data streams
from slow slaves can be interrupted to occasionally
transport the data from fast slaves. Sep-
September 2009 16
Figure 1. Block diagram
ARM1178JZF-S
arate unidirectional read and write channels as
well as the support of unaligned data transfers
also accelerate the communication via AXI. AXI
is defined for bus widths of up to 1024 bits. In
current systems nowadays, we find bus widths
of 64 bits. The advanced high-performance bus
also supports large bus bandwidths and a high
data throughput, but offers less flexibility with
the management and control of several masters
as well as with the optimization of data streams
on the bus. The advanced peripheral bus on the
other hand is used to integrate peripherals with
a low bandwidth requirement and speed in the
processor architecture. It relates to a simple bus
system with which only addresses, data and status
of the data transmission are communicated.
A further important part of the ARM1176JZF-
S core is its memory management unit (MMU).
The MMU not only monitors the write and
read accesses to the respective memory. Its key
functions also include the transmission of virtual
memory addresses to physical addresses, a
function that amongst others is needed by the
operating systems, as well as monitoring and
management of access rights. The latter take
place according to the guidelines of the ARM
TrustZone technology. This technology enables
the integration of applications for which
the privacy of the users must be protected. Mobile
online banking should be mentioned here
as a possible application.

Figure 2. Example AXI system
Figure 3. S3C6410X block diagram
In addition to 32-bit ARM and 16-bit THUMB
instruction sets, the ARM1176JZF-S core also
supports 8-bit JAVA byte codes. ARM Jazella
technology is utilized thereby to support Java.
This serves as basis for a multi-tasking Java virtual
machine and enables simple and efficient
implementation of applications written in Java.
ARM1176JZF-S core users also benefit from the
ARM instruction set that has been enhanced
with several interesting DSP functions. These
include, in addition to multiply-andaccumulate
(MAC) operations or the support
of saturation arithmetic, instruction sets for the
processing of multimedia data. This is essentially
due to utilization of SIMD (single instruction
multiple data) instructions. SIMD allows
optimized access to two 16-bit or four 8bit
values, which are jointly stored in a 32-bit
register. The values are processed simultaneously
and independently of each other. Carryovers
have no effect on the 32-bit register. In addition,
sum of absolute difference (SAD) instructions
are provided for the MPEG processing.
A vector floating point unit was integrated
in the core for additional acceleration of computing
operations. Furthermore, the ARM11
architecture offers the user a high level of debug
and boundary-scan functionality. A powerful
JTAG interface serves as interface to the ARM
debug tools. The integrated embedded trace
macrocell (ETM) allows tracing of processor
values, without restriction of computing power.
In addition, an EmbeddedICE-RT logic, which
allows a variety of breakpoints, is integrated in
the core.
What in practice can be done with the ARM11
core, such as the ARM1178JZF-S, is clearly
shown in the example of the S3C6410 controller.
It has three different AXI buses. The 64bit
wide system bus (AXI_SYS) is operated with
maximum 133 MHz. The other two AXI buses
serve as access to AHB or directly to SFRs. All
peripherals such as memories and sub-bus systems,
which require a high and fast data
throughput, are connected here. A further 32bit
wide AHB serves as interface to an APB for
less high-performance peripheral components
such as timers, serial interfaces or I/Os. The
AHB, as with the AXI, is operated with maximum
133 MHz and the APB with 66 MHz. In
addition to serial interfaces such as UART, SPI
and I2C, amongst others, five 32-bit timers with
two PWM outputs including dead-time generator
are on the chip. The integrated watchdog
monitors the functionality of the system, and a
real-time clock plus calendar functionality
with extra voltage supply ensures the correct
time, also in the energy save mode. A 2-port
USB 1.1 host controller and a USB 2.0 OTG
controller with high-speed, full-speed and low-
MICROCONTROLLERS
speed support are integrated as a modern
communication interface to the outside world.
With seven peripheral blocks for memory
management, the S3C6410 storage system supports,
amongst others, NAND-flash, NORflash,
SD-RAM, DDR-RAM and mobile
SDRAMs / DDR-RAMs. Furthermore, the chip
offers a PC card controller and ATA controller.
Portable storage media, such as secure digital
cards (SDCs) and multimedia cards (MMCs),
can also be integrated directly in the application
via the appropriate on-chip controllers. Particularly
worthy of emphasis are the wide range of
audio functions. The integrated AC97 controller
works according to the AC97 V2.0 standard
and has a stereo input, a mono microphone
input and a stereo output. It communicates
via the AC-LINK interface with an additional
external analog front end chip such as
Analog Devices’ AD1819. The digital I2S audio
interface supports up to 24-bit audio with a
maximum sampling rate of 192 kHz. Simple
audio A/D and D/A converters, but also external
systems for audio processing or ICs with integrated
EQs and amplifiers such as TI’s
TAS5707, can be connected to this interface. In
addition to the standard I2S interface, an I2S
multi-audio interface is also located on the chip,
which enables 5.1 surround sound. It only remains
to mention the mono PCM send/receive
block, which supports a 16-bit PCM 2-port
audio interface.
Furthermore, for preparation and processing of
complex graphics data, a 2D graphics accelerator
and a 3D graphics accelerator have been
implemented on the S3C6410. The 2D graphics
accelerator supports drawing and pixel operations.
Among other things, the 3D graphics
accelerator allows OpenGL ES 1.1 and OpenGL
ES 2.0 rendering. Furthermore, especially notable
are the programmable Vertex and Pixel
Shaders and the 32-bit floating-point pipeline.
The hardware JTAG codec processes image formats
up to a maximum of UXGA. In addition,
the device enables encoding up to YCbCr4:2:2
and decoding up to YCbCr4:4:4. As a result,
image material, irrespective of whether it is generated
from the application or read in via the
integrated camera interface, can be effectively
and quickly processed.
The outputting of image data can optionally
take place via a TV-out signal or via the integrated
TFT LCD controller. For this purpose,
the S3C6410 provides a composite video output
and a S-video output. The TFT LCD interface
supports resolutions from 320 x 240 pixels up
to a maximum of 1024 x 1024 pixels, alpha
blending, overlay, scaling and zooming. The
common NTSC and PAL formats are available,
whereby a TV scaler and a preprocessor ensure
optimization of the image data. ■
17 September 2009

MICROCONTROLLERS
Low-power microcontroller design
using the ARM Cortex-M0 core
By Rob Cosaro, NXP Semiconductors
This article discusses the low
power characteristics of the
ARM Cortex-M0-based
LPC1100 microcontroller
series, and the system design
techniques that minimize the
amount of energy consumed
from a power source.
In order to understand the power consumption
of a microcontroller, it is important to understand
the basic components of dissipation of a
CMOS device. There are two major categories
of consumption; dynamic consumption and
static consumption. Dynamic power consumption
of a CMOS device to a first order is
defined as
Figure 1 shows a diagram of a simple CMOS inverter.
When this inverter switches, it must
charge or discharge the load capacitance, which
dissipates power. The load capacitance is a combination
of the interconnect capacitance and the
gate capacitance of all the devices it is driving.
If the device is not switching, all that is consuming
power is the leakage current of the device.
Therefore for a given process geometry the
dissipation varies as the square of the voltage
and linearly with frequency. The characteristic
that power consumption varies linearly with
frequency gives rise to a commonly quoted
number for microcontrollers, which is current
consumption per MHz. For low-power devices
this is given as μA/MHz and ranges from
200μA/MHz to over 300μA/MHz. These numbers
are somewhat misleading since there is no
standard on how the measurements are taken.
The key point is how much work is performed
for the current consumed or, for a more comprehensive
measurement, how much energy is
consumed for a given calculation. Since this
type of measurement is not widely used yet, the
μA/MHz metric is used in this discussion.
The amount of current used per MHz by the
digital CMOS structures is not the only aspect
of the current consumed by the device: there
are analog circuits that are required to support
the digital domain. These can be classified into
the timing components, power control components,
memories and peripherals. The timing,
power control and memory components
are part of the microcontroller platform and are
not optional, but the analog peripherals are part
of the feature set and will differ across the microcontroller
family. Table 1 shows the timing
September 2009 18
components used in the LPC1100. The table is
arranged from lower to higher power consumption.
As with all analog design there is a
trade-off between accuracy and the amount of
current it consumes. The LPC1100 has a flexible
scheme for controlling these components
that can trade off consumption versus accuracy
so they can be tailored to the application.
The current consumption for the core is not
just about the slope but also the offset current
that comes from the analog components that
are required to support the core. This is sometimes
referred to as the zero-Hertz current.
Since the LPC1100 has a flexible clocking architecture
this current is not fixed. As the frequency
is lowered, switching off the clocking
components that are not required to generate
the required operating frequency can reduce the
offset current. As an example the LPC1100 can
be operated on the loose low-power oscillator
from 0 to 1MHz and then the more accurate in-
Timing components Attributes
Low power internal osc Low frequency, Low accuracy, Low power
Internal RC oscillator Accuracy better than 1%
Crystal oscillator High accuracy low jitter.
DLL Fast start-up, higher jitter, low consumption
PLL Slow start-up, low jitter. Moderate consumption
Table 1. LPC1100 timing components
Picture by Ernst Rose,
Pixelio

Figure 1. CMOS power dissipation
Figure 2. Average current
MICROCONTROLLERS
ternal RC oscillator can be turned on to provide the frequency from 1
to 12MHz. Leakage consumption is the current that the CMOS junction
draws when the digital logic is not switching. This current is highly
dependent on the process node and then on how the libraries in the
node are optimized. For the LPC1100 the libraries are optimized for low
leakage. Giving the user different power-down options can further optimize
leakage. Besides the leakage of the CMOS junctions, various analog
features can also be controlled in these modes.
Sleep mode turns the clocks off to the core but the user has the option
to leave on peripherals. The power in this mode is not just leakage but
dynamic current of the peripherals that are left on. In this mode data
can be still received, but the core retains its state and can continue operation
when required. In power-down mode all clocks to the digital
logic are turned off and the analog sub-systems can be controlled to
have flexible wake-up times depending on the application requirements.
The lowest power mode is when all the analog clocking elements are
turned off. Wake-up time is determined by the selection of the wakeup
clock source. The fastest time is from the low-power oscillator and
the slowest time is from the crystal oscillator and the PLL. In deep
power-down mode power is turned off to the internals of the microcontroller,
except a small always-on domain. The always-on domain has
a set of registers that can store the information about what happened
before the microcontroller when into deep power-down mode. Wakeup
from this mode occurs either through a wake-up pin or reset.
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MICROCONTROLLERS
Figure 3. Duty cycle effect on battery life
The LPC1100 uses the new Cortex-M0 core
from ARM, which has a big impact both on dynamic
current and as leakage current. Focusing
on a simple instruction set reduces dynamic
current. The M0 mostly uses thumb instructions.
These are 16-bits wide and are interpreted
by the core as 32-bit instructions. The
core also uses a simplified bus interface to reduce
gate count and minimize clocking. In addition,
the core is architected to take advantage
of clock gating and simplified library elements.
Taking all this into account the core is
rated at less than 70μA/MHz. As was previously
stated, this number is somewhat meaningless
since it does not include any information
about how much work can be done with this
current. However, the M0 core is rated at 0.8
DMIPS/MHz, which is a higher rating than an
ARM7 core. Using this core further enhances
the leakage current since the gate count is
equivalent to 8- and 16-bit cores. Since leakage
current is proportional to gate count any savings
in core logic has a big impact.
How the microcontroller power modes are used
depends on the application. If the power source
is always there but has limited capacity, the microcontroller
may be always clocked. The
LPC1100 can change frequency on the fly depending
on processing demand. The LPC1100
current consumption at 30 MHz is specified at
6mA. This can be reduced to a little over
200μA when running at 1 MHz on the lowpower
internal oscillator. However, many applications
that need to minimize consumption
must rely on the power-down and deep power-
September 2009 20
down modes. These applications spend most of
their time in a quiescent state waiting to
process data. The processor must wake up
quickly, process the required data, and then go
back to the quiescent state. Many of these applications
are battery-powered where a low average
current is important to extend battery life.
In order to lower the average current it is important
to be able to process the data as quickly
as possible to reduce the duty cycle. Since the
M0 is a 32-bit processor it can perform the calculations
much quicker than small-width
processors. Figure 2 shows how processing
performance affects the average current. The
figure assumes the peak current and the powerdown
currents are the same for the various
processor types. The M0 core has the capability
to use one half to one fourth the average current
of processors of lower bit widths. The M0
allows the LPC1100 to achieve peak currents of
200μA/MHz.
Lowaveragecurrentiscriticaltoextendbattery
life. This means low quiescent current and small
duty cycles. The LPC1100 has deep powerdown
current of less than 300nA and peak currents
of 200μA/MHz. Figure 3 shows the effects
duty cycle has on battery life. The battery used
for these calculations is a 230mAh lithium button
cell. This plot shows the effect that quiescent
current has on battery life and the kind of
duty cycles that are required to exceed three
years. The average current assumes a peak current
of 2mA which means the LPC1100 is operating
at 10 MHz. It also includes the effects of
start-up time since lowering quiescent current
extends start-up time. If the LPC1100 deep
power-down mode is used, then for 1ms of processing
time out of a period of 200ms a 3-year
battery life is possible. ■
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16-bit microcontrollers with
■ To meet the requirements of the next generation
of microcontroller applications, Renesas
have developed the new high-performance 16bit
H8STiny microcontroller family. The
H8STiny family achieves new levels of real-time
performance, with many new automated peripheral
functions to remove load from the
CPU. The MCU family will be available first in
64- and 80-pin packages with up to 256 kbytes
of on-chip flash and 16 kbytes of on-chip
SRAM.
Each member of the H8STiny family has a selection
of powerful timers, with up to two
motor control timers, a quadrature decoder
timer for position sensing, an on-chip RTC and
a watchdog timer. Devices are available with up
to two high-speed ADC modules on chip,
each of which can be synchronised and controlled
by the on-chip timers. System integration
features include two on-chip oscillators, a
clock halt detection circuit, and an on-chip low
voltage detection (LVD) and power-on-reset
circuit (POR) and a multitude of low-power
options.
With this in mind, Renesas has designed a completely
new real-time event-handling structure
which has been implemented in some of the
latest versions of the H8 micro-controller. This
new structure allows the hardware of the chip
itself to handle many of the real-time events
that in the past would have required CPU intervention.
This new structure creates three
types of event inside the microcontroller, generated
from any external or internal interrupt
source. These can include a wide variety of realtime
stimuli, such as an input pin state changing,
a timer timing out or a byte arriving in a serial
interface.
The device implements standard interrupts,
using a 4 priority level interrupt controller,
however as can be seen, you also have a choice
of generating an automatic data transfer using
the data transfer controller (DTC) instead of an
interrupt, or an event using the event link controller
(ELC). You can choose to generate any
one of these or any combination of these in response
to any real-time event in the micro-controller.
However the real benefit of this device
is in handling such events using either the DTC
or the ELC, as these are then handled without
any software or CPU time, and are thus executed
both faster, and without any software
overhead.
The data transfer controller (DTC), provides
much the same functions as a DMA controller,
as it is designed to allow the transfer of
one or more bytes between memory and a peripheral,
or a peripheral and memory, the
transfer being triggered by an event on the chip.
However it is designed to be both much cheap-
MICROCONTROLLERS
new real-time event handling structure
By Graeme Clark, Renesas
This article describes a new
microcontroller family with a
new real-time event-handling
structure allowing the chip
hardware to handle many of
the reat time events that
would have previouslyrequired
CPU intervention.
er to implement and much more flexible than
a DMA controller. It achieves this by using the
CPU logic to make the transfer, rather than a
large block of dedicated hardware. The advantage
of this is that it is programmable, it holds
its set-up information in a small block of on
chip SRAM and so the DTC controller can be
used not just to create one or two channels of
data transfer, but 10 or 20 if required. The disadvantage
is that the CPU is stopped for a few
cycles while this transfer takes place.
The DTC can transfer 1 byte or more than one
byte, between a peripheral and memory, or
memory and a peripheral, up to 256 times. The
address in memory can be the same address or
it can be incremented or decremented, so creating
a buffer structure. At the end of the transfer,
the DTC can generate an interrupt, to tell
the CPU the data is ready, or in fact, it can trigger
a second DTC transfer, In fact this can be
used to chain a number of transfers together if
required.
The DTC can also be placed into repeat mode,
where it will repeat the transfer an additional
number of times. In this case, we are using the
ADC in scan mode, reading 4 ADC channels
and storing the result in separate result registers.
After the 4th reading is complete, the ADC
module generates an interrupt request, which in
these cases is used to initiate a DTC transfer.
21 September 2009

MICROCONTROLLERS
Figure 1. A simple example of the use of the event link controller
Figure 2. Comparison of the process flow of using the event link controller against the use of
interrupts
After the CPU finishes executing the current instruction,
the DTC controller will take over
control of the bus. The DTC controller reads
the control data held in SRAM corresponding
to the ADC (12 bytes per DTC channel) which
contains the start and destination address of the
data as well as how many bytes and the type of
transfer. Then it initiates the transfer of 8 bytes
into the SRAM, incrementing the address for
each transfer.
The DTC controller then writes back the status
into the SRAM and releases the CPU to execute
the next instruction. The whole transfer process
in this case takes 31 clock states, from start to
finish. If we made this transfer using an interrupt,
when you take into account the interrupt
response time, the time required to transfer the
data, and the return from interrupt, the CPU
would take a minimum of 131 cycles to do the
transfer, so the data transfer controller is almost
four times faster. We also have the added
bonus of requiring no software to make the
transfer, so saving a little code space. For most
applications the flexibility of the DTC provides
a perfect compromise, between speed, flexibility
and of course device cost. You can create automated
transfers between any peripheral and
memory almost without limit. The data transfer
controller provides a method for automating
the transfer of data between peripherals and
memory, while the second new method of handling
device events uses the event link controller
(ELC). The event link controller is designed to
allow device events to automatically cause actions
on the chip. For instance the ELC can start
a timer, or an A/D conversion, or even toggle an
I/O pin, completely automatically.
The event link controller comprises four main
modules, the peripheral event controller for the
peripherals, the timer event input controller, the
port event controller and the event generation
timer. The peripheral event controller allows
the user to choose which peripheral is controlled
by which event. This allows for instance
September 2009 22
the overflow from a 16-bit timer to start the
ADC. The timer event input controller selects
what each timer will do when it is triggered by
an event.
One of the most powerful features of the event
link controller is the ability to generate events
from the I/O ports. On the H8STiny, I/O ports
3 and 6 have this function. The port pins can be
used individually or in groups of 4 pins. Each
pin or group of pins can be used to generate an
event, which then can control other functions
on the chip. However they can also be themselves
controlled by the event link controller.
When an event is generated, you can for instance
choose to toggle a pin or group of pins,
or drive them to a specific logic level. Behind
each group of pins, there is also a port buffer,
you can use an event to drive the contents of
this buffer onto the pins, and if required, rotate
the buffer ready for the next event. This type of
feature is ideal for generating output waveforms
of various types, such as for driving stepper
motors and LCD displays. You can also use this
buffer to latch the input values on the pin when
an event occurs.
The final functional block is the event generation
timer, this is a dedicated 4-channel timer
which allows you to generate up to 4 regular
events, each of which can be used to trigger an
action on the chip. So if you have any function
that requires regular operation, for instance if
you want the ADC to sample every 50msec, or
an I/O pin to toggle every 800nsec, then you
can set up the event timer to generate such a
regular event.
The combination of these features allows the
developer to automate a number of the realtime
elements in his system. An event will take
4 clock cycles from the time it is recognised before
the resulting action starts, for instance an
I/O pin toggling or a timer making a capture.
This feature alone enables the users to handle
many real-time events in hardware on the
chip automatically, without the overhead of
CPU intervention.
A simple example of the use of the event link
controller is shown in figure 2. An external interrupt,
causes a timer to start, after the timer
overflows, this then causes the ADC to start a
conversion. When this system is implemented
on a typical microcontroller, it requires 3 interrupts,
one for the external interrupt, one for
the timer overflow interrupt and one for the
ADC end of conversion, with the resulting CPU
overhead, and of course the software required
for each Interrupt service routine. The system
will also experience some jitter, especially if the
system is using an operating system, which may
be handling a higher priority task when one or
more of these interrupts occur. In the H8STiny,

the whole function can be handled by the
event link controller. After the event link controller
is initialised the whole process can be
handled automatically, without any CPU involvement
until the complete process is finished.
We can compare the process flow of using the
event link controller against the use of interrupts
in figure 2.
In a typical microcontroller, after each interrupt
is generated, we have to service each interrupt,
this results in a delay, and depending on the
software some jitter. In the H8STiny with the
event link controller, each event triggers the
next peripheral automatically. The CPU is
only interrupted after the ADC has finished. So
in this example we have no jitter, as each
■ Atmel expands 6-pin picoPower AVR
MCU family
Atmel announces three new 6-pin picoPower
AVR microcontrollers. The ATtiny4, ATtiny5,
and ATtiny9 are targeted towards size and cost
constrained high volume consumer applications
requiring processing power and low current
consumption. These new devices are all
pin and code compatible, offering a rich feature
set including 512bytes or 1K byte of programmable
Flash memory, 32 bytes of internal
SRAM, 4-channel 8-bit A/D converter (in ATtiny5),
analog comparator, and a 16-bit timer
with PWM.
News ID 315
■ Toshiba: 8-bit MCU drives LCDs with
up to 2560 pixels
Toshiba Electronics Europe has announced a
new 8-bit microcontroller that combines high
performance operation with a variety of integrated
peripherals and the ability to drive 80
segment LCD displays with up to 2560 pixels.
Based on Toshiba’s TLCS-870/C1 core, the
peripheral starts 4 clock cycles after the generating
event, and is not affected at all by the condition
of the CPU, whether it is handling a priority
task or not. We also have the additional
saving that apart from the initialisation, there is
no software required for this process, so code
space required for the application is reduced.
We could also go even further to automate this
example and reduce CPU load, by using the
DTC. We could automatically transfer the data
from the ADC into a buffer in SRAM. Therefore
we could choose to interrupt the CPU perhaps
only after every 100 or 200 readings. The combination
of the data transfer controller and the
event link controller means that many low-level
tasks, especially those based around the I/O and
timers, can be handled automatically without
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Product News
new MCU is capable of processing one
instruction per clock cycle, which helps to
maximize performance and keep power
consumption to a minimum.
News ID 1523
■ TI introduces new femtocell DSP family
Texas Instruments announces a new family of
DSPs enabling residential and enterprise femtocell
manufacturers and service providers to
reduce development time and deliver new
products to market quickly. TI’s family of
multicore femtocell solutions includes a full
portfolio of complementary analog solutions,
support for Linux, and software solutions
from TI third parties, Continuous Computing
and mimoOn.
News ID 1535
■ Microchip: Embedded Designer’s Forums
in UK and Ireland
Microchip announces the opening of registration
for its Embedded Designer’s Forum, a
worldwide series of technical learning events
MICROCONTROLLERS
CPU intervention. This both reduces the load
on the CPU and greatly reduces the system reaction
time to external events. In many systems
todaywearebeingaskedtoaddmoreandmore
functions while still maintaining and even improving
the real-time operation of the system.
The H8STiny is the first device from Renesas to
combine the event link controller and the data
transfer controller, which can be used together
to remove much of the real-time response requirements
of the system, and can automate
many of these low- level and repetitive tasks.
These devices have been aimed at a wide range of
communications and control applications such as
motor control, measurement applications and
low power modems and many others. ■
focused on innovative technologies that will
help designers stay ahead in today’s competitive
environment. The forums will run from
October 2009 through February 2010 at 120
locations across the world, with 51 forums
located in Europe and 6 forums across UK
and Ireland running in November and
December.
News ID 389
■ Freescale: i.MX processor with mixed
signal technology
The i.MX233 applications processor from
Freescale Semiconductor provides an systemon-chip
solution to meet the power and
performance requirements of eBooks, portable
media players and other mobile consumer
electronics applications requiring graphical
user displays. Additional applications include
VoIP handsets, smart remotes, home
appliances, audio peripherals/accessories and
simple human machine interface systems for
industrial applications.
News ID 319
23 September 2009

MICROCONTROLLERS
Minimizing ownership cost for motor
applications by energy saving
By Josef Limmer, Infineon Technologies
This article reviews a new
generation of microcontrollers
which enable energy-efficient
control of brushless DC
motors, permanent magnet
synchronous AC motors and
AC induction motors,
achieving major savings in
electricity costs.
■ In industrial nations more than half of all
electrical energy is consumed by electric motors.
They account for two-thirds of industrial
electric consumption and about a quarter of
residential electric use. Improving the efficiency
of electric motors can therefore save energy
and reduce operating costs. Because of this,
energy efficiency should be a major consideration
designing a motor drive, in place of the
usual “What’s the price of the motor?” A new
generation of microcontrollers enables the energy-efficient
control of brushless DC motors
(BLDC), permanent magnet synchronous AC
motors (PMSM) and AC induction motors,
and delivers a significant contribution to the
overall reduction of energy consumption.
The cost of ownership of an electric motor arises
mainly as electricity cost. Over the lifetime of
a motor, electricity accounts for more than 90
percent of the total cost, including the original
purchase price and maintenance costs. According
to the US Department of Energy
(DoE), using a motor with about 4 to 6 percent
higher efficiency rating can pay for itself in just
two years, if it is in operation for more than
4,000 hours a year. For example the price of a
typical 200W BLDC motor is about 100 euros,
which is about 30 percent more than a comparable
but less efficient brushed motor. Even exchanging
an existing motor is not possible, or
would require a very high investment, it makes
sense to optimize the driving controller and/or
algorithms. In a typical industrial facility the
electrical motors are responsible for approximately
two-thirds of the total electrical energy
consumption. To improve the efficiency and
lower the operating costs, certain rules need to
be observed. These are: select a high efficiency
motor, select the right size of motor, select the
appropriate motor technology, and use appropriate
control algorithms.
Efficiency drops dramatically when motors
are operated below 40 percent of full rated load.
Therefore the right size of the motor is important
to reduce the operating costs. Motors
should be sized to operate with a load factor between
65% and 100%. The common practice of
over-sizing results in less efficient motor operation.
Various motor technologies like brushed DC
motors, brushless DC motors (BLDC), stepper
motors or AC induction motors offer different
benefits on purchase costs, control design, operating
costs and energy efficiency. The type of
motor control used for the application has a big
impact on energy efficiency. For low-power applications,
stepper motors and brushed DC
motors are popular due to their low purchase
price and simple control circuitry, but they provide
somewhat lower energy efficiency and
therefore higher operating costs. Using BLDC,
September 2009 24
PMSM or AC induction motors combined with
powerful motor control algorithms running on
optimized microcontrollers offers the most
energy-efficient solutions. For brushless motors,
a wide range of motor control system algorithms,
including trapezoidal, sinusoidal, and
field-oriented control (FOC), are available.
The simplest but lowest-performance method
is trapezoidal control or block commutation,
also known as six-step control. For each of the
six commutation steps, the motor drive provides
a current path between two windings
while leaving the third motor phase disconnected.
This method has performance limitations
in the form of torque ripple, which causes
vibration, noise, mechanical wear, and reduced
servo performance. Brushless motor
control requires knowledge of the rotor position
and mechanism to commutate the motor.
Typically Hall effect sensors are used to provide
absolute position sensing of the rotor. This results
in more wires and higher cost. Sensorless
BLDC control eliminates the need for Hall effect
sensors, using the back-EMF of the motor
instead to estimate the rotor position. Sensorless
control is essential for low-cost variable
speed applications such as fans and pumps. Refrigerator
and air conditioning compressors
also require sensorless control when using
BLDC motors

Figure 1. Principle of block commutation, sinusoidal commutation and sensorless FOC (from right to left)
Sinusoidal control, also known as voltage-overfrequency
(V/f) commutation, eliminates some
of the issues with block commutation. A sinusoidal
controller drives the three motor windings
with currents that vary smoothly. This eliminates
the torque ripple issues and offers smooth rotation.
The fundamental weakness of sinusoidal
commutation however is that it attempts to control
time-varying motor currents using a basic
proportional-integral (PI) control algorithm
and does not account for interactions between
the phases. As a result, interaction between the
phases causes performance loss at high speeds.
Sinusoidal commutation produces smooth
motion at slow speeds, but is inefficient at high
speeds. Block commutation can be relatively efficient
at high speeds, but causes torque ripple
at slow speeds. This leads to FOC, which provides
the best of both worlds. Using FOC the efficiency
of an electrical motor can be increased
by up to 95%, providing less power consumption,
less noise and excellent torque dynamics.
This results in a better efficiency of the inverter,
a smaller power stage and smaller motor
dimensions at the same torque.
The FOC algorithm works by removing time
and speed dependencies and allowing the direct
and independent control of both magnetic flux
and torque. This is done by mathematically
transforming the electrical state of the motor
into a two-coordinate time-invariant rotating
frame using mathematical formulas known as
Figure 2. Scalable application kits: a complete portfolio of
reference systems for motor drive applications is available,
supporting the whole range of algorithms from block commutation
to FOC.
the Clarke and Park transformations. FOC can
be used on both AC induction and brushless
DC motors to improve their efficiency and
performance. It can be applied also to existing
motors by upgrading the control system.
The effective implementation and execution of
the innovative motor control concepts needs an
optimized microcontroller architecture and
easy-to-use tools. Infineon not only offers
powerful 8-, 16- or 32-bit microcontrollers, but
also provides complete solutions with the related
tool chain. In addition a broad portfolio
of application kits, which ease the evaluation
and implementation of hardware and software
solutions for high-efficiency motor drives, is
offered. Depending on the application a complete
range of MCUs with 8-, 16- and 32-bit
performance up to 400 MIPS is available.
The XC800 MCUs are based on the popular
8051 CPU. It offers scalable solutions with 4
Kbytes to 64 Kbytes flash memory, high-speed
10-bit ADC, PWM unit and packages with 20
to 64 pins. In addition the XC886, XC878 and
XC888 series are equipped with a 16-bit vector
computer supporting FOC, as an industry first
for 8-bit MCUs. Using the vector computer
only about half of the CPU performance is
needed to implement FOC, which is also
unique in the industry. The XC800 MCUs are
ideal for cost-optimized and energy-efficient
low-end drives in fans, pumps, appliances, air
conditioners, etc.
The real-time signal controllers
(RTSC) of the XE166 family are
built around an enhanced C166S
V2 core. High CPU performance
with up to 100 MIPS, a MAC-unit
for DSP functions, enhanced I/O
capabilities, flexible power management
and new peripherals
such as universal serial interface
(USIC) make the XE166 devices
the product of choice for demanding
industrial applications
such as motor control, power supplies,
transportation and communication.
With features like
standard FOC support, dual
MICROCONTROLLERS
motor control, dynamic load response and zero
speed control, the XE166 family is ideal for
usage in inverters, servo drives, escalators or
forklifts.
At the high end the 32-bit devices TC1167 and
TC1197 focus on the most demanding industrial
drives and offer highest performance for
motion control, such as multi-axis systems.
The application kits and tool chain provided
support the fast implementation of the new
motor control techniques on the microcontrollers.
A complete portfolio of reference systems
for motor drive applications is available,
supporting the whole range of algorithms
from block commutation to FOC. All application
kits offered contain a free tool chain
(compiler, real time debugging environment,
etc) and offer plug-and-play design, as all related
hardware and software parts are provided.
A complete solution with microcontrollers,
power semiconductors and passive components
is provided. Complementary comprehensive
documentation with hardware design examples
is included, the application kits serving a voltage
range from 12V to 230V and drive currents
from 200mA to 20A for motors such as stepper,
BLDC and PMSM.
The kits are ready to be used with DAvE Drive,
a unique auto code generator for motor drives.
DAvE Drive is an application code generator
available for the 8-bit MCU families of the
company - support for XE166 is under development.
It helps to reduce the software development
time for motor drives due to fast and
easy configuration of complex control algorithms
like FOC. Designers of motor controls
can quickly focus on application-specific software,
such as the programming of drive functions.
The DAvE Drive software tool generates
complete algorithms with documented source
code and does not derive from precompiled
libraries. It also enables fast adaption for customer-specific
motors. The motor type can be
selected from a library or defined by setting the
key characteristics such as nominal voltage,
phase inductivity or resistance. Using DAvE
Drive the parameters for speed and current
control can be easily adapted. ■
25 September 2009

TESTING &DEBUGGING
New approaches simplify testing and
debugging of complex MCUs
By Heiko Riessland, pls
The IEEE 1149.1 (JTAG)
standard no longer meets all
the demands, in terms of
speed, pin-count and
robustness, for debugging and
testing modern microcontrollers
and complex SoCs. This
article describes new developments
which promise considerable
improvements for
debugging, flash programming
and system test.
■ Microcontroller systems usually need to be
accessed during the total lifecycle, and the hardware
and software tools requirements certainly
differ in each phase. During the development
phase, fastest possible communication with the
target, effective use of on-chip debug resources
and use of the debug interface also for flash
programming, automated testing, calibration,
profiling, etc are at the forefront. During the
production phase, system access is primarily required
for flash programming and testing.
Fast programming algorithms for short production
times, a high level of safety through
various steps of verification, and flexible integration
in typical production and test environments
are decisive here. During the field
maintenance phase, in addition to safety aspects,
an application-specific user interface as
simple as possible for the service personnel is
particularly important.
Optimally meeting all the different requirements
is in practice difficult. Even the popular
IEEE 1149.1 (JTAG) for debugging microcontrollers
shows increasing weaknesses. The IEEE
1149.1 standard that has been in use for almost
twenty years no longer meets all the demands,
in terms of speed, pin count and robustness, for
debugging and testing of modern microcontrollers
and highly complex SoCs. Reducing the
number of pins necessary for debugging is a
motivation for manufacturers to look for new
solutions. With JTAG, we are talking here
about a minimum of five signal pins (TDI,
TDO, TCK, TMS and TRST). Furthermore, a
complete debug interface specification contains
additional signals for target reset, target reference
voltage and manufacturer-specific signals
for the on-chip debug system. Each additional
pin causes costs and is no longer available for
the actual function of the microcontroller.
The frequently offered option to use pins functionally
or alternatively as debug interface is,
however, only a compromise that often proves
to be impractical. Incidentally, the user also
benefits from the reduction of necessary signals
for debug access. The usually tight space on the
production board and costs for the necessary
connectors have, up to now, mostly resulted in
omitting the debug interface completely or providing
it only as an option. However, fewer signal
pins generally also mean reduced space requirement
and smaller connectors.
Another reason for the search for new approaches
is the problem, particularly in field
use, of the connecting cable between the microcontroller
target and the debug tool frequently
being too short. JTAG clock frequencies
of up to 100MHz are possible with modern 32bit
microcontrollers. For that reason, signal
conditioning is necessary after 25 to 30cm. Indeed,
this can ideally take place, as also with the
JTAG-extender of the pls universal access device
September 2009 26
Figure 1. Universal access
device 2+ with JTAG-extender
2+ (UAD2+), with a small converter close to the
target and subsequent forwarding of the reconditioned
signals over differential signal
lines (figure 1). In any case, initial hardware belonging
to the debug solution is needed close to
the target. Hence, the familiar picture of debug
Figure 2. Block diagram of device access port (DAP)

solutions from different manufacturers with
very short ribbon cable close to the enclosure.
A third important aspect that plays a major role
in manufacturers’ current considerations is
the enhancement of stability and ruggedness
with increasing transmission frequency and
bandwidth. With the classic IEEE 1149.1 JTAG
standard there is no protection of the protocol
against disturbing influences on the transmission
lines. Provision for this was not made
when the standard was developed, because at
that time the transmission rate was limited to
40MHz and it was assumed that the components
to be tested were always housed on a
board. It is not surprising therefore that an increasing
number of processor and tool manufacturers
are looking for new approaches. It appears
that Infineon’s device access port (DAP),
ARM’s serial wire debug (SWD) interface and
the vendor-independent IEEE 1149.7 (compact
JTAG) standard are particularly promising.
With device access port, used by Infineon in all
new microcontroller designs of the
XC2000/XE166, TriCore and XC800 families,
the number of pins necessary for the transmission
of the debug protocol has been reduced
as standard with respect to JTAG from five to
two. Consequently at present the implementation
takes place in parallel to the still existent
JTAG interface. These two pins are a clock line
(DAP0) as well as a bidirectional signal line
(DAP1). The JTAG pins TMS and TCK are
thereby alternatively used between JTAG and
DAP (figure 2).The other three JTAG pins that
are no longer necessary can be functionally
used by the application, for example, as port
pins. In this way, the user gets a high flexibility
for the changeover to DAP. In addition, for situations
in which high-speed transmission via
differential lines (LVDS) is needed, Infineon can
optionally resort to a 3-pin variant with one
clock line (DAP0) and two unidirectional signal
lines (DAP1 and DAP2). Furthermore, for
microcontrollers with a very low pin count, another
variant with only one signal line (single
pin DAP – SPD) is specified. This, however,
only covers a reduced transmission bandwidth.
A combination of DAP and SPD on one chip as
well as a parallel implementation of JTAG and
DAP is also possible. This provides the user
with a high level of flexibility.
For safety reasons, the debug interface with previous
implementations is normally switched off
after a power on reset. Switching on is possible
via applicable reset circuitry or also via the
start-up software. The required reset circuitry
can be realized on the target itself or on the
debug connector. The choice of the required
debug mode (2-pin DAP, 3-pin DAP or JTAG)
is possible by means of the pins via the debug
tool or again via the start-up software. The
maximum DAP clock rate can be up to 80
MHz. Thus despite the reduced pin count, at
least the same transmission performance is possible
as with classic JTAG. In addition, the DAP
interface has a low latency, in the microseconds
range, and the communication is very robust.
On the one hand, this is achieved by a 6-bit
checksum (CRC) integrated in the protocol. On
the other hand, the protocol is constructed so
that, for example, a write operation from the
host to the target is acknowledged from it. Unexpected
changes in the target condition or
transmission disturbances can therefore be reliably
recognized by the tool. DAP and JTAG are
pure interfaces that are essentially, especially
with microcontrollers from Infineon, for
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TESTING &DEBUGGING
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(OCDS), whereby its functionality via both
ports is fully usable. For example, unrestricted
read and write accesses to the memory, also
during the run-time. This enables periodical
recording of application data or of the instruction
pointer to the run-time. In addition,
the implemented debug logic allows code
breakpoints and data breakpoints with complex
trigger conditions. Furthermore, for code trace
and data trace, special emulation devices can be
used, whose footprint and functionality do not
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27 September 2009

TESTING &DEBUGGING
Figure 3. Function profiling based on instruction pointer trace
Figure 4. DAP and SWD adapter (opened)
additional on-chip emulation logic. In combination
with special tools, e.g. pls universal emulation
configurator, complex measurements
such as performance analysis, profiling and
code coverage, can be carried out with these
"emulation devices".
ARM has pursued an interesting route with the
serial wire debug (SWD) interface. SWD is part
of a complete package of new debug and trace
techniques, compiled under the name Core-
Sight. There are already the first implementations
in Luminary Micro (now Texas Instruments)
devices with Stellaris Cortex-M3 core
and in the STM32 family from STMicroelectronics.
However, the CoreSight IP can also be
used in all other ARM and Cortex cores. Due to
its wide range of advantages, a further expansion
of its use is very probable. In addition to
the classic JTAG port, which here also remains
available as an alternative, the serial wire mode
offers a 2-pin debug interface. The established
strict separation of debug port by ARM, optionally
JTAG or SWD, and the actual access
port, in other words the access to on-chip
debug hardware, enables a simple exchange
while maintaining all functions. A feature is the
combined serial wire JTAG debug port (SWJ-
DP), which is available to both interfaces via pin
multiplexing. In the serial wire mode, TCK
functions as clock line and bidirectional data
are exchanged via TMS. The changeover takes
place via defined TMS sequences.
Provided that a SWJ-DP is implemented by the
MCU manufacturer, the TDO signal can be
used for the output of different trace results via
a single pin, which in turn results in minimum
chip costs. Via the so-named serial wire viewer
(SWV), among other things instrumentation
trace (printf-like Debugging), watchpoint trace,
instruction pointer trace (figure 3) and event
trace (Interrupt) can be displayed, for which
reason this type of low-cost trace is mainly
found with Cortex-M based microcontrollers.
The maximum possible speed of the SWD interface
is independent from the core clock used
and virtually only limited by the basic technology.
The integrated parity check of the telegram
guarantees a reliable transmission. An additional
acknowledge field (ACK) contained in
the SWD protocol ensures correct execution of
the operation. The new vendor-independent
IEEE 1149.7 (compact JTAG or cJTAG) standard
was ultimately developed to meet current
and future demands of board and system tests.
September 2009 28
IEEE 1149.7 offers additional new features to
support power management, application debug
and device programming while maintaining
full backward compatibility with the existing
IEEE1149.1. A total of 6 classes are defined,
which can be implemented by IEEE 1149.7
compatible TAP controllers (TAP.7). Class 0 defines
the adherence to 1149.1 compatibility,
Class 1 enables additional command protocol
for reset and power management, Class 2 offers
the capability of BYPASS for chip internal TAPs
for optimization of the shift chain, Class 3 defines
the capability of star coupling several
TAP.7 controllers, Class 4 provides new scan
protocols on the basis of only two signal lines,
and Class 5 allows the use of up to two application-specific
data lines e.g. for real-time
trace. Classes 4 and 5 are especially interesting
for embedded applications where cost and
performance are particularly important. On the
one hand here also, as with both of the other solution
approaches presented, only two pins are
needed for the communication. On the other
hand, the data throughput is considerably increased
by various optimized scan protocols.
The IEEE1149.7 standard is still new and corresponding
implementations are rare.
According to this writer's understanding, a
complete synthesizable IP core for cJTAG is so
far only available from IPextreme. Other various
committees including NEXUS and MIPI,
which are also involved with debug interfaces,
will certainly take the cJTAG standard into account.
Meanwhile, most microcontroller users
agree that the almost twenty-year old JTAG
standard is only suitable to a limited extent to
meet today’s demands for speed, pin count and
robustness. However, the question remains;
what is the ideal future solution?
As the described examples show, different manufacturers
and interest groups are following similar
fundamental principles in the search for an
answer, but there is certainly no real standardization.
Therefore, the challenge for debug and
test tools consists of support for all new interfaces.
A prerequisite for such universally usable
and at the same time commercially acceptable
solutions is certainly, in addition to a modular
adapter concept for different connectors (figure
4), also a flexible tool architecture. With special
FPGA equipped debug devices, such as pls universal
access device 2 (UAD2), it is already today
possible to implement nearly all debug protocols
without much additional effort. ■
www.embedded-control-europe.com
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How to perform integration
testing of embedded software
By Frank Büchner, Hitex
With temporal component
testing, Tessy provides a
powerful and flexible way to
perform integration testing of
embedded software.
Paramount is the possibility to
specify time in the natural
units of the specification.
■ What does integration test of embedded
software mean exactly? To get inside this term,
we need to specify the objects to be integrated.
As we are talking about embedded software, we
can assume functions in the sense of C as objects.
It is trivial to do integration testing of two
functions in a calling hierarchy, but what about
two functions that do not call each other? A
simple example of two functions which are not
in a calling hierarchy but should be tested integrated
together are push() and pop() of the
abstract data type stack. The isolated testing of
push() or pop() is unit testing but that is not
sufficient here - integration testing is needed.
Integration testing would consist of a sequence
of push() and pop() calls. The input for such a
test case is formed by the parameter values of
push() and the initial contents of the stack. The
results are the return values of pop() and the
final state of the stack. In the case where calls to
push() and pop() could result in additional
calls, e.g. to error-handling functions, such calls
also belong to the expected results of an integration
test case.
In the following, we use the term component to
denote the set of functions that we want to test
in an integrated form. This includes also the
data on which the functions jointly operate. IEC
61508 uses the term module for such a component.
A component test case, as described for
the stack, is called a scenario. In the case where
we know that one of the functions of a component
is called at equidistant points in time,
we are able to use these calls as a basis for a simulation
of time. Then temporal conditions
can be tested in a scenario. This is called
temporal component testing.
Figure 1 depicts a component with its functions
and its data. Some of the functions (depicted in
dark blue) can be called from the outside of the
component (indicated by the green arrows);
calls to these functions form the stimulating
part of a scenario. These functions are designated
component functions. There might be
other functions inside the component (depicted
in light blue), that are not visible outside the
component. The functions in a component do
not need to be in a (single) calling hierarchy. A
component can comprise data, which is accessible
from outside the component. Hence,
Figure 2. Interface of the component
TESTING &DEBUGGING
Figure 1. Example of a
component
during a scenario execution, data can be written
(i.e. supplied as test input) or read (i.e. retrieved
as test result). The result of a scenario
execution can consist of calls to functions in
other components, i.e. calls to functions outside
the component (indicated by the red arrows).
The red heart in figure 1 marks one of the component
functions as the heartbeat function. Obviously,
component testing is a good integration
test for the functions inside the component. In
the next application, a car interior light, we take
the interior light of a car as example for component
testing and use Tessy to execute the tests.
Tessy is a tool to automate the unit, module,
and integration testing of embedded software.
The interior light is controlled by two sensors.
Firstly a sensor indicating if the door is closed
or open, secondly a sensor indicating if the ignition
is on or off. The (very rudimentary)
specification for the behaviour of the interior
lightrequiresittogoonassoonasthedooris
closed. If nothing else happens, it must go off
automatically after 5 seconds at the latest.
However, should the ignition be switched on
during these 5 seconds, the interior light should
go off immediately.
As a start, Tessy determines automatically the
interface of the component by analyzing the
source code of the component (figure 2). The
upper part of figure 2 lists all the functions of
the component that can be called from outside
29 September 2009

TESTING &DEBUGGING
Figure 3. Scenario with result (left hand side) and call trace (right hand side)
Figure 4. Another scenario and result (left hand side) and call trace (right hand side)
the component and thus can be part of a scenario
(component functions). The function
init() initializes the component. The two functions
set_sensor_door() and set_sensor_ignition()
pass the state of the respective sensors to
the component. The function tick() forms the
heartbeat function of the component. This was
manually set by the user; it is indicated by a
special icon placed before tick(). The middle of
figure 2 depicts the function calls from the
component to functions in other components
(external function calls). These are the two
functions LightOn() and LightOff(), which
switch the interior light on and off, respectively.
During component testing, Tessy replaces
LightOn() and LightOff() by stub functions, i.e.
we do not need implementations of these two
functions for testing. The lower part of figure 2
(variables) depicts the variables of the component
which are accessible during a scenario
execution. The arrows indicate if a variable can
be input, or output, or both. Now the desired
integration test cases (or scenarios) are created.
In Tessy this is done in the so-called scenario
editor (SCE). Interface elements (figure 2) are
dragged to a time scale and dropped on the desired
point in simulated time. If needed, values
for parameters of functions or for variables can
be specified. The scenario in figure 3 tests that
the interior light is switched on immediately
after the door was closed. Because ignition is
not operated in this scenario, it is expected that
the interior light is switched off after 5 seconds
at the latest. For the example at hand, we and
the component assume that tick() is called
every 10 ms. This gives us a basis for the simulation
of time. Prior to the first call to tick(), i.e.
before 0ms of simulated scenario time, init() is
called. This call arranges for a defined initial
state, in our case door open, ignition off, and
September 2009 30
light off. After the third call of tick(), i.e. at 30
ms of simulated scenario time,
set_sensor_door() is called with the parameter
value closed. This indicates for the component
that the door is closed, which should cause
some actions. Two expected actions are specified
in the scenario. Firstly, LightOn() must be
called after the next call to tick(), i.e. at 40 ms
simulated time. Secondly, LightOff() must be
called after 5 seconds at the latest, i.e. between
30 ms and 5030 ms of simulated scenario time.
The execution of the scenario yields the expected
results. This is indicated by the green tick
marks in the scenario (left hand side of figure
3) and is also illustrated by the call trace (right
hand side of figure 3).
In this scenario, the distance between two subsequent
calls to tick() is specified to be 10 ms.
This allows Tessy to calculate the distance in
time, given in natural units (e.g. seconds) for
the corresponding number of calls to tick().
Should the distance change, Tessy automatically
recalculates the number of calls. This is especially
useful, if the distance is changed in the
courseoftheproject,e.g.from10msto20ms,
e.g. because 10 ms is not longer sufficient for all
the work to be done in that time frame. With
Tessy, time always is specified in the natural
units of the specification and not in implementation-dependent
values.
The scenario in figure 4 tests if the interior light
is switched off after the ignition was switched
on. Different to the scenario in figure 4, init() is
not called. This can remain undone because
Tessy is able to set/check the value of a variable
prior, during and after a test. This feature is
used to mimic the init() call. This feature
would also allow starting a scenario from an
invalid state or checking that init() works correctly.
Another difference to the first scenario is
that the operation of the ignition is indicated
using a variable (and not by calling set_sensor_ignition(),
as one might assume from the
first scenario). Furthermore, the second scenario
specifies that the interior light shall go on
after the door is closed and shall go off immediately
after the ignition is switched on. Tessy
determines the code coverage achieved by the
execution of the scenario(s). ■
October 8, 2009 – 10h00 to 17h00 CET
(Central European Time)

PRODUCT NEWS
■ MSC: new variations of Qseven platform
MSC has announced new variations of its Qseven platform MSC Q7-
US15W. The main features of all three versions like graphics, high definition
audio and the interface offering, e.g. USB and Gbit Ethernet, are
identical. The high end version comes with the 1.6GHz Intel Atom
Z530 processor, 1024MB of SDRAM, two SATA-300 ports and three
PCI Express x1 lanes.
News ID 1617
■ Avalue: multiple IPC chassis for Mini-ITX boards
Avalue brings out a series of chassis for housing the components of IPCs
which allow secure mounting and protect from vibration, static and
other harmful elements. Avalue offers a range of industrial chassis types
from VESA compliant rack-mount chassis, wall-mount chassis to desktop
chassis.
News ID 1622
■ Brainboxes launches range of USB to serial products
Brainboxes launches its new range of USB to Serial connectivity devices,
releasing two new products. The RS232 and RS422/485 serial devices
provide a highly efficient and robust serial port extension suitable for
office and laboratory environments. This will ensure that desktops and
laptops supplied with limited or no serial ports continue to have connectivity
to a wide range of RS 232 and RS 422/ 485 devices via USB.
News ID 382
■ Kontron: evaluation kit for compact COM Express class
The Kontron microETXexpress evaluation kit offers developers a fast
introduction into the compact class of COM Express. The Kontron microETXexpress
Starterkit is an all-round development platform for a
wide range of embedded applications that require high-performance
and processing density on a compact footprint with low-power consumption.
It is ideal for evaluating applications that are to be operated
on small mobile devices which are battery-powered or even solarpowered
and small embedded devices which have a compact format
while offering a high level of features.
News ID 1602
■ ADLINK: EBX SBC based on 1.6 GHz Intel Atom N270 processor
ADLINK announces the LittleBoard 735 EBX SBC based on the ultra
low power Intel Atom N270 processor at 1.6 GHz, code name ‘Diamondville’.
The LittleBoard 735 supports the 1.6 GHz Atom’ N270
processor with Intel 945GSE chipset (‘Navy Pier’ platform) and provides
a DDR2 533 SODIMM socket for up to 2 GB of RAM. Independent
10/100BaseT and 10/100/1000BaseT Ethernet ports give system OEMs
flexibility.
News ID 304
■ AAEON: ETX CPU module with VIA C7/Eden processors
AAEON announces the new Embedded Technology eXtended product
ETX-CX700M, which is based on the VIA C7/ Eden (V4) series
processors combined with the VIA CX700M chipset. The ETX-
CX700M provides support for a multitude of expansion and storage interfaces
that will allow for numerous options to be designed onto the
baseboard.
News ID 1560
■ Wind River adds virtualization to multicore software solution
Wind River announces the immediate availability of Wind River Hypervisor,
a key pillar of Wind River’s comprehensive Multicore Software
Solution for device development. Wind River Hypervisor is a high-performance
Type-1 hypervisor, which supports virtualization on single
and multicore processors.
News ID 1482
31 September 2009

PRODUCT NEWS
■ DFI: Atom-based micro COM Express
module
DFI announces a new fanless Micro COM Express
module, the NP905-B16C, conforming to
COM Express Type 2 Basic form factor standard,
but with a smaller size of 95 x 95 mm. The
Micro COM Express form factor uses the same
220-pin high-speed SMT connectors and signaling
of the COM Express Type 2 Basic module,
making it a drop-in replacement. The DFI
NP905-B16C module is based on the Intel
Atom N270 processor with 533MHz FSB and
Intel 945GSE Express chipset with ICH7M I/O
controller hub.
News ID 1529
■ Quadros supports Atmel SAM9
microcontrollers
Quadros Systems announces support for the
AT91SAM9G20 and SM9XE microcontrollers
from Atmel. Quadros Systems’ offers one-stop
development and run-time solutions for Atmel
SAM9 microcontrollers combining RTXC
RTOS and integrated software with MDK-
ARM development tools from Keil, an ARM
company.
News ID 311
■ Logic Technology: file system for Windows
CE, Windows Mobile and VxWorks
Logic Technology announced availability of
Datalight’s Reliance Nitro fault-tolerant embedded
file systems. Reliance Nitro is now
available for Windows CE and Windows Mobile
as well as VxWorks, and is reported to boost
sequential and random write speeds as much as
five times faster than the default file systems.
News ID 1555
■ Keil supports STM32 Connectivity Line
Keil announces support for the STM32 Connectivity
Line in the Keil MDK-ARM Microcontroller
Development Kit and RL-ARM Real-
Time Library. Keil has also introduced the new
MCBSTM32C evaluation board and starter kit.
The STM32 Connectivity Line is based on the
ARM Cortex-M3 processor and features fullspeed
USB OTG, dual CAN2.0B interfaces, and
10/100 Ethernet including hardware support
for IEEE1588 Precision Time Protocol. The devices
share common peripherals with other
STM32 families, thereby allowing easy project
migration, and have up to 256KB Flash and
64KB SRAM.
News ID 1652
■ pls: Eclipse plug-in for Universal Debug
Engine
A special plug-in, now provided with the Universal
Debug Engine 2.6 from pls Programmierbare
Logik & Systeme at no extra cost, enables
a separate debug perspective for Eclipsebased
platforms. The tool, offered as a feature
installation package, offers the advantage that
the complete functionality of the UDE as cross
debugger under Eclipse is retained without having
to compromise. It can be simply installed
with Eclipse’s own mechanism. Operation in
"RCP stand-alone application mode" is also
possible.
News ID 357
■ IAR: KickStart Kit for NXP Cortex-M3
devices
IAR Systems has introduced a KickStart Kit for
NXP’s ultra-low power ARM Cortex-M3 device,
the LPC1768. The kit, which includes IAR
Embedded Workbench for ARM and example
applications to speed up development of
LPC1768 designs, consists also of a development
board fitted with the microcontroller,
evaluation editions of IAR PowerPac for ARM,
IAR visualSTATE, and a separate IAR J-Link
debug probe for ARM.
News ID 1648
■ Lauterbach supports Intel Atom processors
Lauterbach announces support for the Intel
Atom processor core based platforms for MID
Menlow, Moorestown and Medfield. The existing
TRACE32PowerDebug system has been
enhanced for the new processor architecture,
bringing a mature high end debugging solution
to the Intel Atom architecture.
News ID 1656
■ Data Modul: 7.6 inch active-matrix OLED
Data Modul offers active matrix OLEDs from
CMEL with high optical performance, even
under extreme viewing angles, characterize
OLEDs.With an active area of 165x99mm the 7.6’
P0760WVLB-T (CM02013) is currently the
largest available active-matrix OLED from CMEL.
News ID 386
■ NXP and Trusted Logic: NFC middleware
integration
NXP and Trusted Logic announce a partnership
in which Trusted Logic will distribute and market
the NFC middleware, which embeds the
NXP Reference Implementation. Under this
More information about each news is available on
www.Embedded-Control-Europe.com/ece_magazine
• You have to type in the “News ID”. —
September 2009 32
agreement, Trusted Logic will license the NXP
Reference Implementation, which has been
validated with the latest NXP NFC controller
PN544. Trusted Logic will enhance the solution
with their Java Specification Request 257 implementation
to enable NFC technology in Java
Micro Edition environments. Furthermore,
this partnership will enable NFC middleware
integration with the most common mobile operating
systems and facilitate integration services
to handset manufacturers.
News ID 1870
■ Actron: SoC NAPs support PCIe and
Gigabit Ethernet
Actron announces two new network appliance
processors from MosChip supporting PCI Express,
Gigabit Ethernet and display interfaces in
a single solution. With MosChip’s MCS8142,
system engineers can target a variety of well
suited applications that include consumer network
attached storage, PC and media docking
stations, SOHO, home network automation,
media servers, and more.
News ID 1940
■ GLYN adds USB solutions from FTDI
to linecard
GLYN has extended its product portfolio with
a line of high quality products from FTDI to
complement existing applications with USB.
FTDI is specialised in developing quick and
easy solutions for USB applications.
News ID 1446
■ Innovasic: Intel CAN controller replacement
Innovasic Semiconductor has announced production
units are shipping for the IA82527.
The IA82527 is a form, fit, and function replacement
for the original Intel 82527 Serial
Communications Controller. The Innovasic replacement
supports the same CAN 2.0 Specification
as the original device, including standard
and extended message frames.
News ID 1456
■ MSC: DDR3 DRAM modules from Samsung
MSC opens the ‘green world’ by launching the
new DDR3 DRAM modules from Samsung.
The Samsung DDR3 delivers a combination of
maximum bandwidth and density at the lowest
power consumption. This high performance,
energy-efficient memory is perfectly suited
when energy efficiency becomes a criteria.
News ID 1676

■ MIPS joins Open Embedded Software
Foundation
MIPS Technologies announces it has joined the
Open Embedded Software Foundation (OESF),
an organization focused on standardization and
development of Android platforms for embedded
devices beyond mobile handsets.
News ID 1562
■ Evatronix and Soft-Mixed Signal: IP
solution for USB 2.0
Evatronix and Soft Mixed Signal announce the
availability of the complete USB 2.0 solution
that integrates USB 2.0 Controller IP from Evatronix
and the USB 2.0 PHY IP from Soft
Mixed Signal.The USB Controller IP implements
configurable amount of memory for
each endpoint, which could also be turned off
for even less power usage, while a common
buffer for OUT type endpoints saves power by
taking less silicon area.
News ID 1899
■ Ericsson expands distribution agreement
with Mouser Electronics
Ericsson Power Modules has extended its distribution
agreement with Mouser Electronics to
include the APAC regions. Mouser is an electronic
component distributor, focused on the
rapid introduction of new products and technologies
to electronic design engineers. Customers
throughout the APAC regions now can
order Ericsson's complete DC/DC converter
range including its latest digitally controlled
converters from Mouser. Mouser currently has
branch locations throughout Asia in countries
such as Singapore, Hong Kong, and China.
Mouser has launched websites and printed catalogs
in multiple currencies and languages.
News ID 1913
■ GLYN is new distributor for RF
modules from Radiocrafts
Radiocrafts appoints GLYN as new distributor
in Germany, Switzerland, Austria and the
BeNeLux area. GLYN is a distributor of hightech
microelectronics and has been in the
market since 1980. The distributor is selling integrated
circuits from leading semiconductor
manufacturers, particularly microcontrollers,
microprocessors, memory components, optoelectronics
and power electronics.
News ID 1601
■ Toshiba: industrial LCD panels with
LED backlight system
Toshiba Electronics Europe has announced
the development of the latest range of activematrix
colour TFT liquid crystal displays for the
industrial market. The new display modules incorporate
light-emitting diode backlight technology
offering long life performance with
100,000 hours mean time between failure.
News ID 354
PRODUCT NEWS
■ Mouser and Multi-Tech: distribution
agreement includes Europe and Asia
Mouser Electronics announces its distribution
authorization with Multi-Tech Systems has been
expanded into a global agreement. Multi-Tech
Systems manufactures telephony, internet, remote
access, and device networking products
that connect voice and data over IP networks.
News ID 1875
■ SEGGER: RTOS supports Freescale’s
Controller Continuum
SEGGER announces that embOS RTOS, is
now available for the 8-bit HCS08 and 32-bit
ColdFire V1 MCUs from Freescale. embOS
comes with a premium feature set such as the
embOSView task-level profiling tool, an unlimited
number of tasks and no need for preconfiguration.
By supporting both cores, SEG-
GER helps developers to easily transfer from the
8-bit to 32-bit world using the Freescale Controller
Continuum.
News ID 1979
■ Evatronix C68000 IP core implemented
by HAPA
Evatronix announces that its C68000 IP core
has been successfully implemented in the
HAPA 100 Controller series for printers of the
Swiss company HAPA. The HAPA 100 controller
series supports 3- and 5-phase stepper
motors in their printers since 15 years. The
printers are used in the pharmaceutical industry
to print by flexographic or drop on demand
technology aluminum foil, blisters and cartons
in line just before packaging.
News ID 1871
■ Eremex: topological router and layout
editor
Eremex presents the TopoR - high-performance
topological router and layout editor
which provides high-quality PCB design of any
complexity with lightning speed as a result of
unique algorithms implementation.
News ID 1675
■ pls: debug tool now available
for Freescale’s i.MX25 family
pls Programmierbare Logik & Systeme now offers
its Universal Debug Engine, which is currently
available for a variety of different ARM7
and ARM9 derivates, also for Freescale’s
ARM926EJ-S core based i.MX25 family of
multimedia applications processors. The intuitive
and configurable user interface of the UDE
provides i.MX25 users with unrestricted C/C++
support, a powerful symbol browser, freely configurable
toolbars, extensive context related
menus and HTML as description language for
application-specific windows. In addition, the
use of standard script languages guarantees a
high level of automation.
News ID 1536
33 September 2009
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info@peak-system.com

PRODUCT NEWS
■Atlantik: RoadTunes ROM solution
for portable navigation devices
Atlantik Elektronik presents the new Road-
Tunes ROM solution from CSR for portable
navigation devices and aftermarket in-car devices,
such as Bluetooth-enabled vehicle infotainment
and car radio platforms. The Road-
Tunes ROM chipset is a complete embedded
Bluetooth solution in a QFN package which requires
minimal external components.
News ID 1667
■ Digi-Key and Fujitsu Microelectronics:
worldwide distribution agreement
Digi-Key has signed a new agreement with Fujitsu
Microelectronics for the worldwide distribution
of Fujitsu's new low-power, lowpin-count,
8-bit microcontrollers and digital
touch-screen sensor ICs. Fujitsu products
stocked by Digi-Key are now available for immediate
shipment via Digi-Key's global websites.
News ID 1882
■ Microchip: 100Mbps Ethernet controllers
with integrated security engines
Microchip announces the ENC624J600, a low
cost standalone IEEE 802.3TM compliant
100Mbps Ethernet interface controller. These
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Ethernet controllers combine a 10/100Base-TX
physical interface and a Media Access Controller
with a hardware cryptographic security
engine, and can connect to any PIC microcontroller
via an industry-standard Serial Peripheral
Interface or a flexible parallel interface.
News ID 1953
■ Infineon: Gigabit PHY complies with
EEE guidelines
Infineon announces an energy efficient Gigabit
Ethernet Physical Layer IC. The new XWAY
PHY11G is compliant with EEE guidelines for
energy efficiency, and it is the industry’s smallest
footprint IC for Gigabit home networking
applications. The new IC targets all major
broadband applications, including xDSL and
PON Routers in home gateway solutions, IP
phones, PC motherboards, and consumer applications
like IP-TVs, IP set-top boxes, game
consoles and printers.
News ID 1946
■ Yamaichi: SD card reader with push/push
system
Yamaichi Electronics now offer the FPS009-
2409-0, a new push/push SD/MMC card connector
replacing the top mount component
FPS009-2405-0. The PCB layout is unmodified
compared to the old version which means that
the new card reader can be used with the existing
layout. The low profile design with its 2.8
mm has almost the same height as the SD card
itself.
News ID 1533
■ Xilinx: Virtex-6 and Spartan-6 evaluation
kits
Xilinx releases the Xilinx Base Targeted Design
Platform aimed at accelerating the development
of SoC solutions with Xilinx Virtex-6 and
Spartan-6 FPGAs. This base-level targeted design
platform combines the 11.2 release of the
ISE Design Suite, expanded intellectual property
portfolio, and pre-verified reference designs
targeting Virtex-6 or Spartan-6 FPGAs within
fully integrated evaluation kits that enable design
teams to dramatically shorten development
cycles and focus engineering resources on creating
greater product differentiation.
News ID 1551
■ Mouser: Actel IGLOO nano FPGAs
and ProASIC3 nano FPGAs
Mouser Electronics announced that it is stocking
Actel’s IGLOO nano FPGAs and ProASIC 3
nano FPGAs. Designed for high-volume applications
where power and size are key decision
criteria, Actel’s IGLOO nano FPGAs are perfect
ASIC or ASSP replacements, yet retain the historical
FPGA advantages of flexibility and
quick time-to-market in low-power and small
footprint profiles.
News ID 1552
September 2009 34
■ Rutronik and FCI sign pan-European
franchise agreement
Rutronik Elektronische Bauelemente and FCI
are extending their partnership to the whole of
Europe. The two companies have been working
together for more than ten years. Up until now,
the distribution cooperation covered Northern
and Eastern Europe as well as France, Italy and
Belgium.
News ID 412
■ NI: open environment for real-time
test system development
National Instruments announces NI VeriStand
2009, an open, configuration-based software
environment for creating real-time testing
applications such as hardware-in-the-loop and
controlled environmental tests. All of the common
functionalities of a real-time test system
are implemented and optimized inside NI
VeriStand in a ready-to-use format, making it
possible for real-time test system developers to
complete their test application development
more efficiently.
News ID 415
■ Toshiba: low-power ARM9 MCU supports
MMI functionality
The latest addition to Toshiba’s family of scalable,
low-power ARM-based microcontrollers
allows designers to quickly and easily add
man-machine interface functionality to their
embedded designs. The TMPA912CMAXBG is
based on the 32-bit ARM926EJ-S core and is
ideal for embedded systems that require integrated
display control and graphic processing
capabilities but do not need all of the performance,
memory and functionality offered by
previous models in the Toshiba ARM9 family.
News ID 1475
■ Altera: low-power FPGA family with
security features
Altera announces a new low-power FPGA
family with security features. The new Altera
Cyclone III LS FPGAs offer the highest logic,
memory, and DSP density per board area.
These devices are the lowest power FPGAs at
less than 0.25W of static power for 200K logic
elements. The Cyclone III LS FPGAs, which are
shipping now, target power and board-spacesensitive
applications in all market segments including
military and industrial.
News ID 1577
■ RS: product range for surveillance
system design
RS Components launches a new product range
for electronic design engineers working on developing
surveillance systems. Over 400 products
have been introduced into the RS portfolio,
covering a wide range of technologies that are
used when creating a new surveillance system.
News ID 1612

■ Wind River enables multilevel secure
systems
Wind River has introduced the VxWorks MILS
Platform 2.0. The platform includes a VxWorks
runtime environment, allowing Wind River
customers to leverage their in-house VxWorks
experts as well as legacy VxWorks application
code within new multilevel secure systems, and
a high-assurance runtime environment for development
of guards, downgraders, and other
components requiring the highest security.
News ID 1503
■ Micro Digital: smxUSB 2.0 stacks for
synopsys USB controllers
Micro Digital has announced the port of Micro
Digital’s smxUSB 2.0 stacks to the Synopsys DesignWare
USB 2.0 OTG host and device controllers.
This makes available to Synopsys’customers
the full arsenal of Micro Digital USB
products, which include, on the device side:
audio, composite, Ethernet over USB, mass
storage, mouse, serial, and multiport serial; on
the host side: audio, CDC ACM, HID, Hub,
mass storage, printer, RFID, serial, USB to Ethernet,
USB to serial, and WiFi with WEP and
WPA. These products interface with Micro Digital
file system and networking products.
News ID 1593
■ CMX: RTOS and file systems for
SAM3U Cortex-M3 processors
CMX Systems announces the availability of its’
CMX-RTX and CMX-TINY+ RTOSes and
CMX-FFS file systems for Atmel’s SAM3U
Cortex-M3 series processors. CMX-RTX is a
truly preemptive, multi-tasking RTOS supporting
a wide variety of 8-, 16-, 32-bit microcomputers,
microprocessors, and DSP's. CMX-
RTX offers the smallest footprint, the fastest
context switching times, and the lowest interrupt
latency times available on the market
today.
News ID 388
■ SEGGER tools fully support STM32
Connectivity line
SEGGER Microcontroller has released middleware
and debugging products for the STM32
Connectivity Line of ARM Cortex-M3 based
microcontrollers from ST Microelectronics.
SEGGER’s complete middleware set includes
embOS RTOS, embOS/IP TCP/IP stack,
emWin GUI, emFile and emUSB. Debugging
solutions include the J-Link emulator and the
brand new J-Trace for Cortex’M3, which enables
instruction tracing via ARM's embedded
trace macrocell.
News ID 1972
Nuremberg
SPS/IPC/DRIVES/
Electric
Automation
PRODUCT NEWS
■ Atmel: evaluation kit for Cortex M3-based
MCUs
Atmel announces the availability of the SAM3U-
EK Evaluation Kit for rapid application development
on ARM Cortex -M3 based Flash microcontrollers
with high-speed 480 Mbps USB + Phy.
In addition to a plug-and-play socket for the highspeed
USB device it features a high speed
SDIO/SDCard/MMC slot, two UART connectors,
a ZigBee radio header, two analog inputs, audio
in- and outputs and a JTAG-ICE debug port.
News ID 1665
■ ADLINK: CoreModule 730 embedded
processor based Atom Z510 and Z530
ADLINK has announced the new CoreModule
730 embedded processor, based on the ultra low
power Intel Atom Z510 and Z530 processors at
1.1 and 1.6 GHz, respectively, which sets a new
efficiency standard for tiny rugged computers
by using the new SUMIT expansion interface.
It reinvents stackable and mezzanine architectures
by packing an enormous amount of data
bandwidth and easy connectivity ‘ including
multiple PCI Express lanes, USB 2.0 interfaces,
LPC bus, I2C bus, and SPI bus ‘ into a fraction
of the space previously occupied by only the 33
MHz parallel PCI-104 bus.
News ID 1891
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www.mesago.com/sps
Mesago Messemanagement GmbH, Postfach 10 32 61, 70028 Stuttgart, Germany, sps@mesago.com, phone +49 711 61946-828

PRODUCT NEWS
■ HCC supports Micron’s 1Gb serial
NAND Flash
HCC-Embedded announces that the entire
HCC product line now supports and interoperates
with Micron Technology’s 1-gigabitbased
serial NAND Flash.The Micron device
used in HCC’s porting and testing work is a
1Gb-based chip providing embedded applications
with the flexibility to easily upgrade their
storage capacity.
News ID 1642
■ MSC presents MachXO control
development kit
MSC announced a new development kit from
Lattice, referred to as the MachXO Control Development
Kit and 6 new reference designs that
will provide a foundation platform for system
control demos scheduled to be released during
the remainder of this year. The kit features the
MachXO LCMXO2280 device, the Power Manager
II ispPAC-POWR1014A device, 2Mbit
SPI Flash memory, 1 Mbit SRAM, interface to
a16x2LCDpanel,SDandCompactFlash
memory sockets, fan circuit, current and voltage
sensor circuits, USB connector, several
LEDs and switches.
News ID 1643
■ SMH: signal multiplexer for device
in-system programming
SMH Technologies unveils a new signal multiplexer
for device in-system programming (MicroPlexer).
Microplexer allows the ISP connection
coming from the programmer/tester to
be switched to one of the available output channels.
In this way, a single programmer/tester can
easily handle multiple device programming,
whether on a single board or distributed across
multiple boards in a panel assembly.
News ID 1513
■ Vector simplifies optimization of ECU
parameters
Vector has released CANape 8.0 ‘ the latest version
of its development software for ECU calibration.
It accelerates optimal calibrating of
ECUs in the vehicle by extended measurement
data acquisition, optimized calibration data
management and new data mining functions
for automated data evaluation. The new
‘Simulink XCP Server’ option will benefit both
functional and software developers with convenient
parameter setting as well as quick access
to measurement variables of the Simulink
model directly in CANape.
News ID 306
■ SMSC: power management solution for
MOST network devices
SMSC announces the MPM85000, a low-cost,
single-chip solution for power management of
MOST devices. Seeing the need to eliminate
several discrete electronic components, SMSC's
MPM85000 combines all necessary peripheral
functions to implement a MOST network interface
such as diagnostics, status monitoring
and power supply.
News ID 1969
■ iC-Haus: 8-channel fail-safe FET
driver with AEC Q100 qualification
iC-MFL from iC-Haus is a monolithically integrated,
8-channel level shifter to drive Logic
FETs. The internal circuit blocks have been designed
in such a way that with single errors,
such as open pins or the short-circuiting of two
outputs, the iC-MFL output stages switch to a
predefined, safe state. Externally connected
FETsthereforeshutdownsafelyintheeventof
a single error.
News ID 385
■ Enea launches Android competence center
Enea is establishing a competence center based
in Lund, Sweden which will offer professional
software development services, as well as a variety
of training programs for developers of
mobile phones, netbooks and mobile internet
devices who are considering using the emerging
open source platform or are actively developing
devices.
News ID 401
■ Infineon: single-chip WLAN ICs for
home gateways
Infineon has introduced a new family of singlechip
WLAN integrated circuits. The new XWAY
WAVE100 ICs provide a solution for wireless
network access points that are compliant to the
802.11n draft standard for data rates up to
150Mbit/s as well as the 802.11 b/g standard.
The single-chip XWAY WAVE100 family integrates
the WLAN Baseband, Media Access
Controller, RF, Low Noise Amplifier and Power
Amplifier functionalities. The XWAY WAVE100
single-chips are available with either SDIO or
PCI interface.
News ID 140
■ TI: high-voltage bipolar DACs for
high-precision test equipment
Texas Instruments introduces a four-channel,
high-voltage, bipolar digital-to-analog converter.
Developed on TI’s HPA07 analog CMOS
process technology, the 16-bit DAC8734 is
part of a new family of high-performance,
bipolar DACs, including pin-compatible 12and
14-bit family members featuring up to six
times lower drift than competing devices along
with the widest operating temperature range
and the highest initial accuracy.
News ID 392
■ Microchip: analogue resistive touch-screen
controllers
Microchip announces the mTouch AR1000
resistive touch-screen controllers. By providing
September 2009 36
built-in decoding and advanced filtering, as well
as controller-driven calibration, the AR1000
controllers lower costs and reduce time to
market for any embedded resistive-touch design.
The AR1000 provides proprietary touchscreen
decoding algorithms that enable applications
to receive fully processed, reliable touch
coordinates.
News ID 1938
■ Avnet Memec: 16-bit, industrial DAC
with high-voltage output circuits
Avnet Memec introduces the new MAX5661 of
MaximIntegratedProducts.Thedeviceisa16bit,
industrial DAC with two precision, highvoltage
output circuits integrating a voltageoutput
amplifier, current-output amplifier,
and pass transistors on the same silicon. The
dual-range voltage-output amplifier provides a
voltage proportional to the DAC value and provides
either a 0 to 10V or -10V to +10V output.
News ID 323
■ NatSemi: dual 16-bit, 160-MSPS pipeline
A/D converter
National Semiconductor introduces a dualchannel
16-bit, 160 mega-samples per second
pipeline ADC. With two high-speed channels,
the ADC16DV160 offers small footprint of 10
x 10 mm and is targeted at multi-carrier,
multi-standard GSM/EDGE, WCDMA, LTE
and WiMAX wireless basestations. The
ADC16DV160 consumes less than half the
power per ADC channel (650 mW) compared
to competing single-channel 16-bit 160-MSPS
pipeline ADCs, while offering a large inputbandwidth
(1.4 GHz).
News ID 309
■ CMX: extended support for RENESAS
SH-2A family
CMX Systems announces the availability of the
CMX-RTX, CMX-MicroNet and CMX-FFS
file systems for the Renesas SH-2A processor
family. SH-2A support is in addition to current
CMX product availability for the SH-1, SH-2
and SH-3 processor families. CMX software
supports SH-2A derivatives with and those
without floating point units.
News ID 1478
■ Lauterbach: TRACE32 PowerProbe for
the NEC’s 78K0R/Kx3
Lauterbach has launched a new high performance
debug probe for NEC Electronics 16-bit
microcontroller family 78K0R/Kx3. Lauterbach’s
TRACE32 PowerDebug for 78K0R provides
an ultra-high-speed interface accelerating
the entire debug process including code download,
flash programming and source code debugging.
The tools can be connected to either
Windows or Linux hosts via USB 2.0 or Ethernet
10/100/1000.
News ID 429

■ iSYSTEM: version 2009 of winIDEA IDE
and debugger
iSYSTEM has released its 2009 version of their
integrated development environment called
winIDEA. The new release integrates a lot of
new hardware and software related features
such as support for new microcontroller families
and their newest derivates, new hardware
and software manuals. Last but not leastwinIDEA
2009 includes iSYSTEM’s Software
Development Kit with support for script languages
such as Phython, TCL, Perl, Automation
Server, LabVIEW, and more for a seemless integration
of iSYSTEM tools in the software development
and test process.
News ID 1500
■ Digi-Key and IAR announce global
distribution agreement
Digi-Key and IAR Systems have entered into an
agreement for the distribution of IAR Systems
development tools for embedded systems. IAR
Systems products stocked by Digi-Key include:
IAR Embedded Workbench ‘ a set of
highly sophisticated and easy-to-use development
tools for embedded applications. It integrates
the IAR C/C++ Compiler, assembler,
linker, librarian, text editor, project manager,
and C-SPY Debugger into an integrated development
environment.
News ID 1489
■ Micro Digital: smxUSB 2.0 for
Synopsys USB controllers
Micro Digital announces the port of Micro Digital's
smxUSB 2.0 stacks to the Synopsys DesignWare
USB 2.0 OTG host and device controllers.
This makes available to Synopsys'customers
the full arsenal of Micro Digital USB
products, which include, on the device side:
audio, composite, Ethernet over USB, mass storage,
mouse, serial, and multiport serial; on the
host side: audio, CDC ACM, HID, Hub, mass
storage, printer, RFID, serial, USB to Ethernet,
USB to serial, and WiFi with WEP and WPA.
These products interface with Micro Digital file
system, networking products, and RTOS.
News ID 1563
■ Green Hills enhances Platform for
Industrial Safety
Green Hills has announced major enhancement
to its Platform for Industrial Safety, adding support
for the Green Hills Secure Virtualization Architecture
and expanding the existing networking,
file system and target hardware options. The
certified INTEGRITY OS technology forms the
core of the Green Hills Platform for Industrial
Safety, a comprehensive solution that also includes
tools, secure guest OS virtualization,
services, and middleware aimed at reliabilitycritical
industrial control, transportation, railway,
nuclear control and automation systems.
News ID 243
■ HCC: SD card validation testing supports
SafeFAT
SafeFAT, HCC’s failsafe FAT12/16/32 file system,
is now supported by HCC-Embedded’s SD card
validation program. Under this program, HCC
ensures that any card that passes the validation
tests is suitable for use with the SafeFAT file system.
SD cards (including MMC, SDv2 and
SDHC cards) are hugely successful storage devices;
they are available everywhere.
News ID 428
■ Xilinx: PCIe FPGA block achieves
PCI-SIG 1-8 lane compliance
Xilinx announces that its newest generation
Virtex-6 FPGA family is compliant with the
PCI Express 2.0 specification, delivering up to
50 percent lower power than previous generations.
The second-generation PCIe block integrated
in Xilinx Virtex-6 FPGAs has passed
PCI-SIG PCI Express version 2.0 compliance
and interoperability testing for 1 to 8-lane configurations.
News ID 1926
■ The MathWorks: tools qualified according
to ISO 26262 standard
The MathWorks announces that its Real-Time
Workshop Embedded Coder 5.3, PolySpace
Client for C/C++ 7.0.1, and PolySpace Server for
C/C++ 7.0.1 products are qualified according to
the ISO/DIS 26262-8 standard. The TÜV SÜD
qualification assessment provides evidence to
automotive engineers using Model-Based Design
with defined verification and validation
measures that the tools are suitable for developing
safety-related software for ISO 26262.
News ID 427
■ Actel: radiation-tolerant FPGAs for
space-flight systems
Actel announces the availability of RTAX-DSP
prototype FPGAs, enabling hardware demonstration
and timing validation of designs targeted
to Actel’s RTAX-DSP space-flight FPGAs.
The RTAX-DSP prototype devices have the
same pin assignment, mechanical footprint and
identical timing properties across the full military
temperature range as their space-qualified
counterparts. RTAX-DSP space-flight FPGAs
add embedded radiation-tolerant multiplyaccumulate
blocks to the tested and proven industry-standard
RTAX-S product family.
News ID 368
■ NI: new version of DIAdem includes
advanced data visualization
National Instruments announces DIAdem 11.1,
a new version of the interactive software for
managing, analyzing, visualizing and reporting
test data that includes new features and filtering
capabilities for advanced development and
automated analysis.
News ID 1631
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37 September 2009

PRODUCT NEWS
■ HCC: embedded USB stacks for
STM32 MCUs
HCC-Embedded releases complete embedded
USB Device, Host and OTG stacks for the
STMicroelectronics STM32 range of Cortex-
M3 microcontrollers. The STM32 family of 32bit
microcontrollers is based on the advanced
ARM Cortex-M3 core, which was developed
specifically for embedded applications. The
STM32 family uses the Cortex-M3 architectural
enhancements, including the Thumb-2 instruction
set.
News ID 131
■ Lauterbach: TRACE32 supports
Fujitsu’s FAMOS RTOS
Lauterbach announces, that its TRACE32 debuggers
support the Real-Time Operating System
FAMOS of Fujitsu Microelectronics.
FAMOS was developed specifically for the
ARM11 based HDTV decoder chipsets of the
series MB86H6x for set top boxes. The FAMOS
awareness is integrated immediately in all new
TRACE32 software versions for the ARM architecture.
News ID 300
■ SEGGER: middleware and debugging
support for AT91SAM3U-EK
SEGGER has released middleware and debugging
products for the AT91SAM3U-EK, Atmel’s
evaluation kit based on the ARM Cortex- M3
based microcontroller AT91SAM3U. SEGGER’s
complete middleware set includes embOS,
embOS/IP, emWin, emFile, emUSB device and
emUSB host. Debugging solutions include the
J-Link emulator and the brand new JTrace for
Cortex’M3, which enables instruction tracing
via ARM's embedded trace macrocell.
News ID 1657
■ STM: 1.5V op-amps with power-saving
features
STMicroelectronics has unveiled three new
families of precision op-amps targeting lowpower
and portable products, with powersaving
features that include high-speed performance
at low supply current, operation
from a 1.5V supply, and device-shutdown capability.
Offering low power consumption,
high bandwidth and good accuracy, the TSV6xx
families serve applications such as portable
medical equipment, instrumentation, signalconditioning
systems, sensor interfaces, and active
filtering.
News ID 1444
■ Hitex: programming solution for
XC2000-based designs
Hitex has launched SpeedFlash-XC, a programming
solution addressing users who will
start the production of their Infineon 16-bit
microcontroller-based design. SpeedFlash-XC
can be integrated easily in the production environment.
The system allows to connect up to
8 SpeedFlash-XC probes to a needle bed production
equipment via JTAG or DAP.
News ID 1670
■ Green Hills enhances Platform for
Medical Devices
Green Hills announced major enhancements to
its Platform for Medical Devices by adding support
for Secure Guest OS virtualization and expanding
the existing networking, file system
and target hardware options. The Platform for
Medical Devices significantly reduces the cost
and risk of Class II and Class III medical product
approval while providing faster time-tomarket
for customers.
News ID 1889
QNX: enhanced support for OMAP35x processors
from TI
QNX Software Systems announces software and
tools support for automotive, industrial automation,
and consumer device customers creating
products based on TI OMAP35x processors.
Designed for products that require rich HMI,
multimedia, and audio capabilities, the support
includes the QNX Neutrino RTOS, the QNX Aviage
Multimedia Suite, the QNX Aviage HMI Suite,
the QNX Aviage Acoustic Processing Suite, and
the QNX CAR reference designs for automotive
infotainment systems and digital clusters.
News ID 1621
■ Microsoft: Windows Embedded technology
preview
Microsoft has released the Windows 7-based
Windows Embedded Standard 2011 Community
Technology Preview to original equipment
manufacturers and developers of specialized devices
worldwide through its immediate public
availability. Windows Embedded Standard 2011
delivers the power, familiarity and reliability of
the Windows 7 operating system in a highly
customizable and componentized form, enabling
OEMs in industrial automation, entertainment,
consumer electronics and other
markets to focus on their core competencies
and create product differentiation.
News ID 398
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Hitex 34
LynuxWorks 9
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Mesago 35
MSC 3
PEAK-System-Technik 33
Rutronik 19
Toshiba 23
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