Placement slides - UCSD VLSI CAD Laboratory
Placement slides - UCSD VLSI CAD Laboratory
Placement slides - UCSD VLSI CAD Laboratory
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ECE260B – CSE241AWinter 2004<strong>Placement</strong>Website: http://vlsicad.ucsd.edu/courses/ece260b-w04ECE260B – CSE241A <strong>Placement</strong>.1 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>VLSI</strong> Design Flow and Physical DesignStageIO Pad <strong>Placement</strong>Power/GroundStripes, Rings RoutingGlobal<strong>Placement</strong>Definitions:•Cell: a circuit component to be placedon the chip area. In placement, thefunctionality of the component is ignored.•Net: specifying a subset of terminals, toconnect several cells.•Netlist: a set of nets which contains theconnectivity information of the circuit.Detail <strong>Placement</strong>Clock Tree Synthesisand RoutingGlobal RoutingExtraction andDelay Calc.TimingVerificationDetail RoutingECE260B – CSE241A <strong>Placement</strong>.2 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> ProblemInput:•A set of cells and their complete information (a cell library).•Connectivity information between cells (netlist information).Output:A set of locations on the chip: one location for each cell.Goal:The cells are placed to produce a routable chip that meets timingand other constraints (e.g., low-power, noise, etc.)Challenge:•The number of cells in a design is very large (> 1 million).•The timing constraints are very tight.ECE260B – CSE241A <strong>Placement</strong>.3 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Optimal Relative Order:A B CECE260B – CSE241A <strong>Placement</strong>.4 Andrew B. Kahng, <strong>UCSD</strong> ©2003
To spread ...A B CECE260B – CSE241A <strong>Placement</strong>.5 Andrew B. Kahng, <strong>UCSD</strong> ©2003
.. or not to spreadA B CECE260B – CSE241A <strong>Placement</strong>.6 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Place to the leftA B CECE260B – CSE241A <strong>Placement</strong>.7 Andrew B. Kahng, <strong>UCSD</strong> ©2003
… or to the rightA B CECE260B – CSE241A <strong>Placement</strong>.8 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Optimal Relative Order:A B CWithout “free” space, the placement problem is dominated byorderECE260B – CSE241A <strong>Placement</strong>.9 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> ProblemA bad placementA good placementECE260B – CSE241A <strong>Placement</strong>.10 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Global and Detailed <strong>Placement</strong>In global placement, wedecide the approximatelocations for cells byplacing cells in global bins.In detailed placement, wemake some local adjustmentto obtain the final nonoverlappingplacement.Global <strong>Placement</strong>Detailed <strong>Placement</strong>ECE260B – CSE241A <strong>Placement</strong>.11 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> Footprints:Standard Cell:Data Path:IP - FloorplanningECE260B – CSE241A <strong>Placement</strong>.12 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> Footprints:CoreReserved areasIOControlMixed Data Path &sea of gates:ECE260B – CSE241A <strong>Placement</strong>.13 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> Footprints:Perimeter IOArea IOECE260B – CSE241A <strong>Placement</strong>.14 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> objectives are subject to user constraints /design style:• Hierarchical Design Constraints• pin location• power rail• reserved layers• Flat Design with Floorplan Constraints• Fixed Circuits• I/O ConnectionsECE260B – CSE241A <strong>Placement</strong>.15 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Standard CellsECE260B – CSE241A <strong>Placement</strong>.16 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Standard Cells• Power connected by abutment, placed in sea-of-rows• Rarely rotated• DRC clean in any combination• Circuit clean (I.e. no naked T-gates, no huge inputcapacitances)• 8,9,10+ tracks in height• Metal 1 only used (hopefully)• Multi-height stdcells possible• Buffers: sizes, intrinsic delay steps, optimal repeater selection• Special clock buffers + gates (balanced P:N)• Special metastability hardened flops• Cap cells (metal1 used?)• Gap fillers (metal1 used?)• Tie-high, tie-lowECE260B – CSE241A <strong>Placement</strong>.17 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Unconstrained<strong>Placement</strong>ECE260B – CSE241A <strong>Placement</strong>.18 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Floor planned<strong>Placement</strong>ECE260B – CSE241A <strong>Placement</strong>.19 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> Cube (4D)• Cost Function(s) to be used• Cut, wirelength, congestion, crossing, ...• Algorithm(s) to be used• FM, Quadratic, annealing, ….• Granularity of the netlist• Coarseness of the layout domain• 2x2, 4x4, ….Netlist GranularityAlgorithmCost FunctionLayout Coarseness• An effective methodology picks the right mix from theabove and knows when to switch from one to next.• Most methods today are ad-hocECE260B – CSE241A <strong>Placement</strong>.20 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Advantages of Hierarchy• Design is carved into smaller pieces that can be worked on in parallel(improved throughput)• A known floor plan provides the logic design team with a large degree ofplacement control.• A known floor plan provided early knowledge of long wires• Timing closure problems can be addressed by tools, logic design, andhierarchy manipulation• Late design changes can be done with minimal turmoil to the entire designECE260B – CSE241A <strong>Placement</strong>.21 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Disadvantages of Hierarchy• Results depend on the quality of the hierarchy. The logic hierarchy must bedesigned with PD taken into account.• Additional methodology requirements must be met to enable hierarchy. Ex.Pin assignment, Macro Abstract management, area budgeting, floorplanning, timing budgets, etc• Late design changes may affect multiple components.• Hierarchy allows divergent methodologies• Hierarchy hinders DA algorithms. They can no longer perform globaloptimizations.ECE260B – CSE241A <strong>Placement</strong>.22 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Traditional <strong>Placement</strong> Algorithms• Quadratic <strong>Placement</strong>• Simulated Annealing• Bi-Partitioning / Quadrisection• Force Directed <strong>Placement</strong>• HybridNetlist GranularityAlgorithmCost FunctionLayout CoarsenessECE260B – CSE241A <strong>Placement</strong>.23 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Quadratic <strong>Placement</strong>Analytical Techniquex3x1x2Min [(x1-x3)x3) 2 + (x1-x2)x2) 2 + (x2-x4)x4) 2 ] : Fx4δF/ F/δx1 = 0;δF/ F/δx2 = 0;Ax = BA2 -1= B =-11 2x3x4x =x1x2ECE260B – CSE241A <strong>Placement</strong>.24 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Analytical <strong>Placement</strong>• Get a solution with lots of overlap• What do we do with the overlap?ECE260B – CSE241A <strong>Placement</strong>.25 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Pros and Cons of QPPros:Very Fast Analytical SolutionCan Handle Large Design SizesCan be Used as an Initial Seed <strong>Placement</strong> EngineCons:Can Generate Overlapped Solutions: Postprocessing NeededNot Suitable for Timing Driven <strong>Placement</strong>Not Suitable for Simultaneous Optimization of Other Aspects ofPhysical Design (clocks, crosstalk…)Gives Trivial Solutions without Pads (and close to trivial withpads)ECE260B – CSE241A <strong>Placement</strong>.26 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Simulated Annealing <strong>Placement</strong>Initial <strong>Placement</strong> Improved throughSwaps and MovesAccept a Swap/Move if it improves costAccept a Swap/Move that degrades costunder some probability conditionsCostTimeECE260B – CSE241A <strong>Placement</strong>.27 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Pros and Cons of SAPros:Can Reach Globally Optimal Solution (given “enough” time)Open Cost Function.Can Optimize Simultaneously all Aspects of Physical DesignCan be Used for End Case <strong>Placement</strong>Cons:Extremely Slow Process of Reaching a Good SolutionECE260B – CSE241A <strong>Placement</strong>.28 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Bi-Partitioning/QuadrisectionECE260B – CSE241A <strong>Placement</strong>.29 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Pros and Cons of Partitioning Based<strong>Placement</strong>Pros:More Suitable to Timing Driven <strong>Placement</strong> since it is MoveBasedNew Innovation (hMetis) in Partitioning Algorithms have madethis Extremely FastOpen Cost FunctionMove Based means Simultaneous Optimization of all DesignAspects PossibleCons:Not Well UnderstoodLots of “indifferent” movesMay not work well with some cost functions.ECE260B – CSE241A <strong>Placement</strong>.30 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Hypergraphs in <strong>VLSI</strong> <strong>CAD</strong>• Circuit netlist represented by hypergraphECE260B – CSE241A <strong>Placement</strong>.31 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Hypergraph Partitioning in <strong>VLSI</strong>• Variants• directed/undirected hypergraphs• weighted/unweighted vertices, edges• constraints, objectives, …• Human-designed instances• Benchmarks• up to 4,000,000 vertices• sparse (vertex degree ≈ 4, hyperedge size ≈ 4)• small number of very large hyperedges• Efficiency, flexibility: KL-FM style preferredECE260B – CSE241A <strong>Placement</strong>.32 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Context: Top-Down <strong>VLSI</strong> <strong>Placement</strong>etcECE260B – CSE241A <strong>Placement</strong>.33 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Context: Top-Down <strong>Placement</strong>• Speed• 6,000 cells/minute to final detailed placement• partitioning used only in top-down global placement• implied partitioning runtime: 1 second for 25,000 cells, < 30seconds for 750,000 cells• Structure• tight balance constraint on total cell areas in partitions• widely varying cell areas• fixed terminals (pads, terminal propagation, etc.)ECE260B – CSE241A <strong>Placement</strong>.34 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Fiduccia-Mattheyses(FM) Approach• Pass:• start with all vertices free to move (unlocked)• label each possible move with immediate change in cost that it causes(gain)• iteratively select and execute a move with highest gain, lock the movingvertex (i.e., cannot move again during the pass), and update affected gains• best solution seen during the pass is adopted as starting solution for nextpass• FM:• start with some initial solution• perform passes until a pass fails to improve solution qualityECE260B – CSE241A <strong>Placement</strong>.35 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Cut During One Pass (Bipartitioning)CutMovesECE260B – CSE241A <strong>Placement</strong>.36 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Multilevel PartitioningClusteringRefinementECE260B – CSE241A <strong>Placement</strong>.37 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Force Directed <strong>Placement</strong>Cells are dragged by forces.Forces are generated by netsconnecting cells. Longer nets generatebigger forces.<strong>Placement</strong> is obtained by either aconstructive or an iterative method.iiF ijjECE260B – CSE241A <strong>Placement</strong>.38 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Pros and Cons of Force Directed<strong>Placement</strong>Pros:Very Fast Analytical SolutionCan Handle Large Design SizesCan be Used as an Initial Seed <strong>Placement</strong> EngineThe ForceCons:Not sensitive to the non-overlapping constraintsGives Trivial Solutions without PadsNot Suitable for Timing Driven <strong>Placement</strong>ECE260B – CSE241A <strong>Placement</strong>.39 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Hybrid <strong>Placement</strong>Mix-matching different placement algorithmsEffective algorithms are always hybridECE260B – CSE241A <strong>Placement</strong>.40 Andrew B. Kahng, <strong>UCSD</strong> ©2003
GORDIAN (quadratic + partitioning)Initial<strong>Placement</strong>min{min{∑∑( x( yii−−xyjj))22}}Partitionand ReplaceECE260B – CSE241A <strong>Placement</strong>.41 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion Minimization• Traditional placement problem is to minimizeinterconnection length (wirelength)• A valid placement has to be routable• Congestion is important because it representsroutability (lower congestion implies betterroutability)• There is not yet enough research work on thecongestion minimization problemECE260B – CSE241A <strong>Placement</strong>.42 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Definition of CongestionRouting demand = 3Assume routing supply is 1,overflow = 3 - 1 = 2 on this edge.Overflow on each edge =Routing Demand - Routing Supply(if Routing Demand > Routing Supply)0 (otherwise)Overflow =Σall edgesoverflowECE260B – CSE241A <strong>Placement</strong>.43 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Correlation between Wirelength andCongestionTotal Wirelength = Total Routing DemandECE260B – CSE241A <strong>Placement</strong>.44 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Wirelength ≠ CongestionA congestion minimized placementA wirelength minimized placementECE260B – CSE241A <strong>Placement</strong>.45 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion Map of a Wirelength Minimized<strong>Placement</strong>Congested SpotsECE260B – CSE241A <strong>Placement</strong>.46 Andrew B. Kahng, <strong>UCSD</strong> ©2003
CongestionMAPECE260B – CSE241A <strong>Placement</strong>.47 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion Reduction PostprocessingReduce congestion globallyby minimizing thetraditional wirelengthPost process the wirelengthoptimized placement usingthe congestion objectiveECE260B – CSE241A <strong>Placement</strong>.48 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion Reduction Postprocessing• Among a variety of cost functions and methods forcongestion minimization, wirelength alone followed by apost processing congestion minimization works the bestand is one of the fastest.• Cost functions such as a hybrid length plus congestiondo not work very well.ECE260B – CSE241A <strong>Placement</strong>.49 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Cost Functions for <strong>Placement</strong>The final goal of placement is to achieve routability andmeet timing constraintsConstraints are very hard to use in optimization, thus weuse cost functions (e.g., Wirelength) to predict our goals.We will show what happens when you try constraints directlyThe main challenge is a technical understanding of various costfunctions and their interaction.ECE260B – CSE241A <strong>Placement</strong>.50 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Prediction• What is prediction ?• every system has some critical cost functions: Area,wirelength, congestion, timing etc.• Prediction aims at estimating values of these costfunctions without having to go through the timeconsumingprocess of full construction.• Allows quick space exploration, localizes thesearch• For example:• statistical wire-load models• Wirelength in placementECE260B – CSE241A <strong>Placement</strong>.51 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Paradigms of Prediction• Two fundamental paradigms• statistical prediction• #of two-terminal nets in all designs• #of two-terminal nets with length greater than 10 in alldesigns• constructive prediction• #of two-terminal nets with length greater than 10 in thisdesign• … and everything in between, e.g.,• #of critical two-terminal nets in a design based onstatistical data and a quick inspection of the design inhand.• “Absolute truth” or “I need it to make progress”• SLIP (System Level Interconnect Prediction)community.ECE260B – CSE241A <strong>Placement</strong>.52 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Cost Functions for <strong>Placement</strong>Net-cutLinear wirelengthQuadratic wirelengthCongestionTimingCouplingOther performance relatedcost functionsUndiscovered: crossingNetlistGranularityAlgorithmCost FunctionLayout CoarsenessECE260B – CSE241A <strong>Placement</strong>.53 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Net-cut Cost for Global <strong>Placement</strong>The net-cut cost is defined as thenumber of external nets between differentglobal binsMinimizing net-cut in global placementtends to put highly connected cells close toeach other.ECE260B – CSE241A <strong>Placement</strong>.54 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Linear Wirelength Cost(x1,y1)1The linear length of a net between cell 1 andcell 2 isl 12 = |x1-x2| x2| +|y1-y2|y2|2(x2,y2)The linear wirelength cost is the summation ofthe linear length of all nets.ECE260B – CSE241A <strong>Placement</strong>.55 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Quadratic Wirelength Cost(x1,y1)1The quadratic length of a net between cell 1 andcell 2 isl 12 = (x1-x2)x2) 2 +(y1-y2)y2) 22(x2,y2)The quadratic wirelength cost is thesummation of the quadratic length of all nets.ECE260B – CSE241A <strong>Placement</strong>.56 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion CostRouting demand = 3Assume routing supply is 1,overflow = 3 - 1 = 2 on this edge.Overflow on each edge =Routing Demand - Routing Supply(if Routing Demand > Routing Supply)0 (otherwise)Congestion Overflow =Σoverflowall edgesECE260B – CSE241A <strong>Placement</strong>.57 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Cost Functions for <strong>Placement</strong>Various cost functions (and a mix of them) have beenused in practice to model/estimate routability and timingWe have a good “feel” for what each cost function iscapable of doingWe need to understand the interaction among costfunctionsECE260B – CSE241A <strong>Placement</strong>.58 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion Minimization and Congestion vsWirelengthCongestion is important because it closelyrepresents routability (especially at lower-levelsof granularity)Congestion is not well understoodAd-hoc techniques have been kind-of working sincecongestion has never been severeIt has been observed that length minimization tends toreduce congestion.Goal: Reduce congestion in placement (willingto sacrifice wirelength a little bit).ECE260B – CSE241A <strong>Placement</strong>.59 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Correlation between Wirelength andCongestionTotal Wirelength = Total Routing DemandECE260B – CSE241A <strong>Placement</strong>.60 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Wirelength ≠ CongestionA congestion minimizedplacementA wirelength minimizedplacementECE260B – CSE241A <strong>Placement</strong>.61 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion Map of a Wirelength Minimized<strong>Placement</strong>Congested SpotsECE260B – CSE241A <strong>Placement</strong>.62 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Different Routing Models for modelingcongestion• Bounding box router: fast but inaccurate.• Real router: accurate but slow.• A bounding box router can be used inplacement if it produces correlated routingresults with the real router.• Note: For different cost functions, answer mightbe different (e.g., for coupling, only a detailedrouter can answer).ECE260B – CSE241A <strong>Placement</strong>.63 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Different Routing ModelsA bounding box routing modelA MST+shortest_path routing modelECE260B – CSE241A <strong>Placement</strong>.64 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Objective Functions Used in CongestionMinimization• WL: Standard total wirelength objective.• Ovrflw: Total overflow in a placement (a directcongestion cost).• Hybrid: (1- α)WL + α Ovrflw• QL: A quadratic plus linear objective.• LQ: A linear plus quadratic objective.• LkAhd: A modified overflow cost.• (1- α T )WL + α T Ovrflw: A time changing hybrid objectivewhich let the cost function gradually change fromwirelength to overflow as optimization proceeds.ECE260B – CSE241A <strong>Placement</strong>.65 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Post Processing to Reduce CongestionReduce congestion globallyby minimizing thetraditional wirelengthPost process the wirelengthoptimized placement usingthe congestion objectiveECE260B – CSE241A <strong>Placement</strong>.66 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Post Processing Heuristics• Greedy cell-centric algorithm: Greedilymove cells around and greedily acceptmoves.• Flow-based cell-centric algorithm: Use aflow-based approach to move cells.• Net-centric algorithm: Move nets withbigger contributions to the congestion first.ECE260B – CSE241A <strong>Placement</strong>.67 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Greedy Cell-centric HeuristicECE260B – CSE241A <strong>Placement</strong>.68 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Flow-based Cell-centric HeuristicCell NodesBin NodesECE260B – CSE241A <strong>Placement</strong>.69 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Net-centric Heuristic2 12 2121ECE260B – CSE241A <strong>Placement</strong>.70 Andrew B. Kahng, <strong>UCSD</strong> ©2003
From Global <strong>Placement</strong> to Detailed<strong>Placement</strong>Global <strong>Placement</strong>: Assumingall the cells are placed at thecenters of global bins.Detailed <strong>Placement</strong>: Cells areplaced without overlapping.ECE260B – CSE241A <strong>Placement</strong>.71 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Correlation Between Global and Detailed<strong>Placement</strong>•WL g: Wirelength optimized globalplacement.•CON g: Wirelength optimized detailedplacement.•WL d: Congestion optimized globalplacement.•CON d: Congestion optimized detailedplacement.Conclusion: Congestion at detailed placement level is correlated withcongestion at global placement level. Thus reducing congestion inglobal placement helps reduce congestion in final detailed placement.ECE260B – CSE241A <strong>Placement</strong>.72 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Congestion• Wirelength minimization can minimize congestionglobally. A post processing congestion minimizationfollowing wirelength minimization works the best toreduce congestion in placement.• A number of congestion-related cost functions weretested, including a hybrid length plus congestion(commonly believed to be very effective). Experimentsprove that they do not work very well.• Net-centric post processing techniques are veryeffective to minimize congestion.• Congestion at the global placement level, correlates wellwith congestion of detailed placement.ECE260B – CSE241A <strong>Placement</strong>.73 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Shapes of Cost Functionsnet-cut costwirelengthcongestionSolution SpaceECE260B – CSE241A <strong>Placement</strong>.74 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Relationships Between the Three CostFunctions:The net-cut objective function is more smooth than thewirelength objective functionThe wirelength objective function is more smooth thanthe congestion objective functionLocal minimas of these three objectives are in the sameneighborhood.ECE260B – CSE241A <strong>Placement</strong>.75 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Crossing: A routability estimator?• Replace each crossing with a “gate”• A planar netlist• Easy to placeECE260B – CSE241A <strong>Placement</strong>.76 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Timing CostCritical PathDelay of the circuit isdefined as the longestdelay among allpossible paths fromprimary inputs toprimary outputs.Interconnection delaybecomes more andmore important in deepsub-micron regime.ECE260B – CSE241A <strong>Placement</strong>.77 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Timing AnalysisLATCH3 2 1 15 5 5192224 4 42 1 3 21LATCHHow do we get the delay numbers on the gate/interconnect?ECE260B – CSE241A <strong>Placement</strong>.78 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Approaches• Budgeting• In accurate information• Fast• Path Analysis• Most accurate information• Very slow• Path analysis with infrequent path substitution• Somewhere in betweenECE260B – CSE241A <strong>Placement</strong>.79 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Timing MetricsHow do we assess the change in a delay due to apotential move during physical design?Whether it is channel routing or area routing, theproblem is the sametranslate geometrical change into delay changeECE260B – CSE241A <strong>Placement</strong>.80 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Others costs: Coupling CostHard to model during placementCan run a global router in the middle of placementEven at the global routing level it is hard to model itAvoid itECE260B – CSE241A <strong>Placement</strong>.81 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Coupling Solutions• Once we have some metrics for coupling, we can calculatesensitivities, and optimize the physical design...Noisy regionExtra spaceGrounded ShieldsQuiet regionSegregationSpacingShieldingECE260B – CSE241A <strong>Placement</strong>.82 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Other Performance CostsPower usage of the chip.Weighted netsDual voltages (severe constraint on placement)Very little known about these cost functions and theirinteraction with other cost functionsFundamental research is needed to shed some light onthe structure of themECE260B – CSE241A <strong>Placement</strong>.83 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Netlist Granularity:Problem Size and Solution Space SizeThe most challenging part of the placement problem isto solve a huge system within given amount of timeWe need to effectively reduce the size of the solutionspace and/or reduce the problem sizeNetlist clustering: Edge extraction in the netlistNetlistGranularityAlgorithmLayout CoarsenessCost FunctionECE260B – CSE241A <strong>Placement</strong>.84 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Layout Coarsening• Reduce Solution Space• Edge extraction in the solution space• Only simple things have been tried• GP, DP (Twolf)• 2x1, 2x2, ….• Coarsen only “easy” partsNetlist GranularityAlgorithmLayout CoarsenessCost FunctionECE260B – CSE241A <strong>Placement</strong>.85 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Incremental <strong>Placement</strong>Given an optimal placement for a given netlist, how toconstruct optimal placements for netlists modified fromthe given netlist.Very little research in this area.Different type of incremental changes (in one region, or all over)Methods to useHow global should the method beAn extremely important problem.ECE260B – CSE241A <strong>Placement</strong>.86 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Incremental <strong>Placement</strong>A placement move changes the interconnectcapacitance and resistance of the associated netA net topology approximation is required to estimatethese changesECE260B – CSE241A <strong>Placement</strong>.87 Andrew B. Kahng, <strong>UCSD</strong> ©2003
“Placynthesis” ” AlgorithmsresizingbufferingcloningrestructuringECE260B – CSE241A <strong>Placement</strong>.88 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Many other Design Metrics:Power Supply and Total Power2.5721.51VddVt6543power0.52101997 1999 2002 2005 2008 201101997 1999 2002 2005 2011Source: The Incredible Shrinking Transistor, Yuan Taur, T. J. Watson Research Center, IBM, IEEE Spectrum, July 1999ECE260B – CSE241A <strong>Placement</strong>.89 Andrew B. Kahng, <strong>UCSD</strong> ©2003
Dual Voltages: A harder problem• Layout synthesis with dual voltages: major geometricconstraintsfeedthrough V HV LGNDV HHLV LL•••HH -- High Voltage BlockL -- Low Voltage BlockLayout StructureINCell Library withDual Power RailsOUTGNDECE260B – CSE241A <strong>Placement</strong>.90 Andrew B. Kahng, <strong>UCSD</strong> ©2003
<strong>Placement</strong> References• C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov, and K. Yan, “Quadratic<strong>Placement</strong> Revisited”,Proc. 34th IEEE/ACM Design AutomationConference, 1997, pp. 752-757• C. J. Alpert, J.-H Huang, and A. B. Kahng, “Multilevel Circuit Partitioning”,Proc. 34th IEEE/ACM Design Automation Conference, 1997, pp. 530-533• U. Brenner, and A. Rohe, “An Effective Congestion Driven <strong>Placement</strong>Framework”, International Symposium on Physical Design 2002, pp. 6-11• A. E. Caldwell, A. B. Kahng, and I.L. Markov, “Can Recursive BisectionAlone Produce Routable <strong>Placement</strong>s”,Proc. 37th IEEE/ACM DesignAutomation Conference, 2000, pp 477-482• M.A. Breuer, “Min-Cut <strong>Placement</strong>”, J. Design Automation and FaultTolerant Computing, I(4), 1997, pp 343-362• J. Vygen, “Algorithms for Large-Scale Flat <strong>Placement</strong>”, Proc. 34thIEEE/ACM Design Automation Conference, 1988,pp 746-751• H. Eisenmann and F. M. Johannes, “Generic Global <strong>Placement</strong> andFloorplanning”, Proc. 35th IEEE/ACM Design Automation Conference,1998, pp. 269-274• S.-L. Ou and M. Pedram, “Timing Driven <strong>Placement</strong> Based on Partitioningwith Dynamic Cut-Net Control”, Proc. 37th IEEE/ACM Design AutomationConference, 2000, pp. 472-476• C.M. Fiduccia and R.M. Mattheyses, A linear time heuristic for improvingnetwork partitions, Proc. ACM/IEEE Design Automation Conference.(1982) pp. 175 - 181.ECE260B – CSE241A <strong>Placement</strong>.91 Andrew B. Kahng, <strong>UCSD</strong> ©2003