Wireless Ad Hoc and Sensor Networks

Optimized Energy and Delay-Based Routing 415optimal routing calculations in energy and delay dependent environments.The use of hardware developed at the University of Missouri–Rolla (UMR)is shown as a development platform for this implementation.Available routing protocols such as data-centric, location-based, QoSaware, and hierarchical for WSNs have been evaluated in simulation.However, there are few, or no, experimental results reported as to howthey perform on hardware. In this section (Fonda et al. 2006), the focus ison hardware implementation of OEDSR protocol and its assessment.This section from Fonda et al. (2006) will present the performance evaluationof OEDSR through hardware implementation. An 8-bit 8051 variantmicrocontroller-based implementation platform utilizing 802.15.4 RF communicationunits is shown. The use of this platform provides high-speedprocessing, interconnectivity with sensors, and a capable RF communicationsunit to facilitate a development platform for WSN. The hardwaredescription includes considerations and limitations that the algorithm andhardware incur on one another. A description of the software implementationis next described.8.10.1 Hardware Implementation DescriptionIn this section, an overview of the hardware implementation of the OEDSRprotocol is given. Use of customized hardware for development of sensing,processing, and networking will be presented. A description of capabilities,limitations, and support for networking applications are given next. Also, inthis section, an overview of the software architectures is given with respectto the routing protocol and its memory requirements on the hardware.Hardware for implementation of the OEDSR was selected to be energyconservative, performance-oriented, and of small form-factor. Use of SiliconLaboratories ® 8051 variant hardware was selected for its ability toprovide fast 8-bit processing, low power consumption, and ease of interfacingto peripheral hardware components. Next, a treatment of the hardwarecapabilities and limitations will be given.Hardware implementation of any algorithm is constrained by the limitationsof the hardware. Use of specific hardware must be weighed againstthe precision, speed, and criticality of an algorithm’s implementation. Constraintsaddressed for the implementation of the OEDSR were the use oflow-power, small form-factor, and fast processing hardware. For this protocol,low power consumption was given the highest priority. In turn, thedemand for low power limits the types of processor architectures that canbe deployed. The selection of the Silicon Laboratories ® 8051 variants wasbased on these criteria. Limitations for the implementation that are incurredthrough the use of the 8051 variant family are a small memory space anda maximum processing speed. In the next section, a description of thespecifications for the hardware-implemented nodes will be given.