Table of Contents - TG Drives

EXTENDED REGISTER GROUPS
SysIo.ADC1 8 0..16383
SysIo, System I/O
System analog input channel #1. Used for resolver #1 cos.
SysIo.ADC2 9 0..16383 R
System analog input channel #2. Normally used for resolver #2
sin.
SysIo.ADC3 10 0..16383 R
System analog input channel #2. Normally used for resolver #2
cos.
SysIo.ADC4 11 0..16383 R
User analog input ANA.In1 raw value.
SysIo.ADC5 12 0..16383 R
User analog input ANA.IN2 raw value.
SysIo.ADC6 13 0..16383 R
System Filtered shunt regulator (Dynamic Brake).
SysIo.ADC7 14 0..16383 R
DC-bus level, raw value. Only valid for 4-10A.
SysIo.PWM0 15 0..255 RW
This PWM output is used to set the resolver excitation
amplitude.
Note. The content of the SysIo.PWM0 register affects both
resolver #1 and #2; since both resolvers are driven from the
same excitation circuitry.
NOTE! Not fully backward compatible from Ver.4.0. or
later.
SysIo.PWM1 16 0..255 RW
NIU
SysIo.PWM2 17 0..255 RW
NIU
SysIo.Sync 18 0..1 RW
Adjustment range:
Time step:
950..1050 Hz
± 400 ns.
Note. Normally the nominal servo cycle is 1000Hz, when the
2
master is another DMC . Using the servo cycle synchronization
mechanism with other master devices running at other
frequencies then remember that all groups with members
where the servo cycle time is used, like speed and
acceleration, will be inaccurate. In other words, speed and
such are calculated assuming a fixed 1000 Hz servo cycle rate.
Enables servo cycle synchronization for slave if 1.
Master should use 0 here.
User's Manual 5.1 Inmotion Technologies AB
Doc. No.9032 0027 01 (B), Rev. 11.07.2001
R
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