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104 Int, Interrupt control Vector.CapInt Vector.CycInt Ireturn in 8 EXAMPLE USAGE . Vector.DI4 , @InDi4Event clr Int.Pend clr Int.SysPend Int.Level , 8 Int.Mask , 8 ; Input event InDi4Event . ireturn in 8 GROUP MEMBERS (GROUP 10) System interrupts vector for captures event. System interrupts vector for cyclical event. Return statement. ;remove pending events ;remove pending events ;positive edge for Di4 ;enable Di4 event EXTENDED REGISTER GROUPS ;return and enable interrupt again Group.Member Member No. Range Ability Default Int.Pend 0 0..65535 RW Pending interrupts from inputs. Bit0 (1) = 1 Pending interrupt from In.Di1. Bit1 (2) = 1 Pending interrupt from In.Di2. Bit2 (4) = 1 Pending interrupt from In.Di3. Bit3 (8) = 1 Pending interrupt from In.Di4. Bit4 (16) = 1 Pending interrupt from In.Di5. Bit5 (32) = 1 Pending interrupt from In.Di6. Bit6 (64) = 1 Pending interrupt from In.Di7. Bit7 (128) = 1 Pending interrupt from In.Di8. Bit8 (256) = 1 Pending interrupt from In.Di9. Bit9 (512) = 1 Pending interrupt from In.Di10. Bit10 (1024) = 1 Pending interrupt from In.Enable. Bit11 (2048) = 1 Pending interrupt from In.PTC. Bit12 (4096) = 1 Pending interrupt from In.Fault. Int.Mask 1 0..65535 RW Bit0 (1) = 1 Enables interrupts from inputs. Enables interrupt from In.Di1. Bit1 (2) = 1 Enables interrupt from In.Di2. User's Manual 5.1 Inmotion Technologies AB Doc. No.9032 0027 01 (B), Rev. 11.07.2001
EXTENDED REGISTER GROUPS Bit2 (4) = 1 Enables interrupt from In.Di3. Bit3 (8) = 1 Enables interrupt from In.Di4. Bit4 (16) = 1 Enables interrupt from In.Di5. Bit5 (32) = 1 Enables interrupt from In.Di6. Bit6 (64) = 1 Enables interrupt from In.Di7. Bit7 (128) = 1 Enables interrupt from In.Di8. Bit8 (256) = 1 Enables interrupt from In.Di9. Bit9 (512) = 1 Enables interrupt from In.Di10. Bit10 (1024) = 1 Enables interrupt from In.Enable. Bit11 (2048) = 1 Enables interrupt from In.PTC. Bit12 (4096) = 1 Enables interrupt from In.Fault. Int.Level 2 0..65535 RW Int, Interrupt control Sets active edge for input interrupts. (Level sampled after possible changes caused by the In.Level variable. ) Bit0 (1) = 1 In.Di1 interrupt active high else active low. Bit1 (2) = 1 In.Di2 interrupt active high else active low. Bit2 (4) = 1 In.Di3 interrupt active high else active low. Bit3 (8) = 1 In.Di4 interrupt active high else active low. Bit4 (16) = 1 In.Di5 interrupt active high else active low. Bit5 (32) = 1 In.Di6 interrupt active high else active low. Bit6 (64) = 1 In.Di7 interrupt active high else active low. Bit7 (128) = 1 In.Di8 interrupt active high else active low. Bit8 (256) = 1 In.Di9 interrupt active high else active low. Bit9 (512) = 1 In.Di10 interrupt active high else active low. Bit10 (1024) = 1 In.Enable interrupt active high else active low. Bit11 (2048) = 1 In.PTC interrupt active high else active low. Bit12 (4096) = 1 In.Fault interrupt active high else active low. Int.SysPend 3 0..65535 RW Pending system interrupts. Bit0 (1) = 1 Pending CycInt interrupt. Bit1 (2) = 1 Pending CapInt interrupt. Bit2 (4) = 1 Pending PosErr interrupt. Bit3 (8) = 1 Pending Ctrl C interrupt. Bit4 (16) = 1 Pending Syserr interrupt. Bit5 (32) = 1 Pending Temperr interrupt. User's Manual 5.1 Inmotion Technologies AB Doc. No.9032 0027 01 (B), Rev. 11.07.2001 105
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HEAD OFFICE INMOTION TECHNOLOGIES A
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Table of Contents Table of Contents
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Related items .....................
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Related items .....................
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Creating/Editing Source Code ......
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12 System architecture register val
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14 B002 Timing and execution flow T
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16 Function Block Diagram SOFTWARE
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18 Function Block Diagram Figure 5.
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20 Function Block Diagram Function
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22 Load a new firmware release SOFT
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24 User's Manual 5.1 Inmotion Techn
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26 Argument types executing results
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28 Mnemonic Operators PL2 NATIVE PO
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30 Compiler Symbols PL2 NATIVE POSI
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32 Compiler directives PL2 NATIVE P
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34 Compiler directives Warnings: No
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36 Spline function compilation dire
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38 Multiline Macro MACRO DEFINITION
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PL2 Mnemonics GENERAL The general f
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PL2 MNEMONICS Standard set Mnemonic
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PL2 MNEMONICS TRACE RELATED MNEMONI
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PL2 MNEMONICS Indexed Addressing Mn
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PL2 MNEMONICS If r_length < r_Membe
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PL2 MNEMONICS Text mode \000 Intern
Page 53 and 54: Extended register groups INTRODUCTI
Page 55 and 56: EXTENDED REGISTER GROUPS STACK HAND
Page 57 and 58: EXTENDED REGISTER GROUPS RD1, Resol
Page 61 and 62: EXTENDED REGISTER GROUPS RD1.FiltSp
Page 67 and 68: EXTENDED REGISTER GROUPS RD2.ChkLow
Page 69 and 70: EXTENDED REGISTER GROUPS Pos Inc Pr
Page 71 and 72: EXTENDED REGISTER GROUPS Pg.ASpeed
Page 73 and 74: EXTENDED REGISTER GROUPS MOTOR, MOT
Page 75 and 76: EXTENDED REGISTER GROUPS 2-Pole: 81
Page 77 and 78: EXTENDED REGISTER GROUPS Motor.Base
Page 79 and 80: EXTENDED REGISTER GROUPS REG, PID R
Page 81 and 82: EXTENDED REGISTER GROUPS GROUP MEMB
Page 83 and 84: EXTENDED REGISTER GROUPS Positive T
Page 85 and 86: EXTENDED REGISTER GROUPS Reg, PID r
Page 87 and 88: EXTENDED REGISTER GROUPS Gear.Incr
Page 91 and 92: EXTENDED REGISTER GROUPS Gear, Elec
Page 93 and 94: EXTENDED REGISTER GROUPS TMR, SYSTE
Page 95 and 96: EXTENDED REGISTER GROUPS Tmr, Syste
Page 97 and 98: EXTENDED REGISTER GROUPS RELATED IT
Page 99 and 100: EXTENDED REGISTER GROUPS SysIo.ADC1
Page 101 and 102: EXTENDED REGISTER GROUPS Bit10 (102
Page 103: EXTENDED REGISTER GROUPS INT, INTER
Page 107 and 108: EXTENDED REGISTER GROUPS Int, Inter
Page 109 and 110: EXTENDED REGISTER GROUPS IN, DIGITA
Page 111 and 112: EXTENDED REGISTER GROUPS X7A:6. In.
Page 113 and 114: EXTENDED REGISTER GROUPS X7B:33. Ou
Page 117 and 118: EXTENDED REGISTER GROUPS Vector, In
Page 119 and 120: EXTENDED REGISTER GROUPS CAPTURE, C
Page 125 and 126: EXTENDED REGISTER GROUPS Ana.ConnTM
Page 127 and 128: EXTENDED REGISTER GROUPS EEPROM Gro
Page 129 and 130: EXTENDED REGISTER GROUPS Bit(0..3)
Page 133 and 134: EXTENDED REGISTER GROUPS RD1CORR, P
Page 135 and 136: EXTENDED REGISTER GROUPS OptAD, ana
Page 137 and 138: EXTENDED REGISTER GROUPS OptAD.7 7
Page 139 and 140: EXTENDED REGISTER GROUPS LAN1, LOCA
Page 141 and 142: EXTENDED REGISTER GROUPS WriteLAN1
Page 143 and 144: EXTENDED REGISTER GROUPS LAN1, Loca
Page 145 and 146: EXTENDED REGISTER GROUPS LAN1, Loca
Page 147 and 148: EXTENDED REGISTER GROUPS LAN1.ErrVe
Page 149 and 150: EXTENDED REGISTER GROUPS MsgObjLAN1
Page 151 and 152: EXTENDED REGISTER GROUPS isrDone: M
Page 153 and 154: EXTENDED REGISTER GROUPS MsgObjLAN2
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EXTENDED REGISTER GROUPS Denominato
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EXTENDED REGISTER GROUPS ABIN Group
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EXTENDED REGISTER GROUPS DSTORE, Gr
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EXTENDED REGISTER GROUPS PARAREA, G
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EXTENDED REGISTER GROUPS XENDAT, Gr
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EXTENDED REGISTER GROUPS wait tmr.t
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EXTENDED REGISTER GROUPS XENDAT.Tra
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EXTENDED REGISTER GROUPS XENDAT, Af
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EXTENDED REGISTER GROUPS XENDAT.RPo
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EXTENDED REGISTER GROUPS Counter 0
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EXTENDED REGISTER GROUPS IDENTIFIER
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EXTENDED REGISTER GROUPS >RPDATA.Ar
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EXTENDED REGISTER GROUPS EXAMPLE US
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EXTENDED REGISTER GROUPS SAnyBus ;
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EXTENDED REGISTER GROUPS GROUP MEMB
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EXTENDED REGISTER GROUPS SAnyBus As
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EXTENDED REGISTER GROUPS PutLONG Pu
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EXTENDED REGISTER GROUPS ABOUTMAIL
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EXTENDED REGISTER GROUPS EN1-EN4, E
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EXTENDED REGISTER GROUPS IENC Group
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EXTENDED REGISTER GROUPS MODEN3-MOD
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EXTENDED REGISTER GROUPS ModEN3.Cap
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200 Computer Mode Record type 1 2 3
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PL2 On line commands PL2 ON LINE CO
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PL2 ON LINE COMMANDS Command name E
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208 B009 Definitions THE ECT MAIN M
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210 Edit in generating this code. F
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212 Compile EXITING EDIT To exit Ed
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214 Test line, assisting the user t
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216 Test including the upload and d
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1 2 3 4 5 6 X7:A 16 15 14 13 12 11
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Start (reset entry) Init If ..... t
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