Analog IC Analysis and Design
Analog IC Analysis and Design
Analog IC Analysis and Design
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<strong>Analog</strong> Integrated Circuits<strong>Analysis</strong> <strong>and</strong> <strong>Design</strong>EE32352010: 5th edition2003<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh1
Lecturer & TA• EE3235 <strong>Analog</strong> Integrated Circuits <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong>• Class room: 資 電 館 206, T7T8R7• Instructor: 謝 志 成 老 師– Office hours: Thur. 4:10pm ~ 5:00pm, or by reservation.– Office : 資 電 館 524B, 03-5162174– Email : cchsieh@ee.nthu.edu.tw– Website: http://www.ee.nthu.edu.tw/cchsieh• Teaching Assistant : 李 其 霖 、 殷 勤 、 邱 衍 智 、 周 韋 帆– Office hours: TBD– Email : 李 其 霖 殷 勤 邱 衍 智 周 韋 帆 <strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh2
Course Description• Course description:– This is a fundamental course for analysis <strong>and</strong> design analogintegrated circuits. It covers quantitative analyses, designconsiderations <strong>and</strong> system applications from circuit <strong>and</strong>physical viewpoints.• Topics:– Modern VLSI technologies, device operations <strong>and</strong> models.– Elementary gain stages.– Current sources.– Frequency responses.– Feedback, stability <strong>and</strong> compensation.– Operational amplifiers.– B<strong>and</strong>gap references.– Switched-Capacitor Circuits.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh3
Syllabus– Week 1 Introduction, CMOS <strong>and</strong> BJT technologies– Week 2 BJT / MOS Device <strong>and</strong> modeling– Week 3-5 Single-stage amplifier, Multi-stage amplifier– Week 6 Differential configuration– Week 7 Current mirrors– Week 8 Output stage– Week 9-10 Feedback2011.04.21 Midterm (Thur, 6:30 pm)– Week 11-12 Frequency response & Stability <strong>and</strong>compensation– Week 13 Introduction of op-amp– Week 14 Two-stage op-amp, Differential op-amp– Week 15-16 <strong>Design</strong> techniques for op-amp– Week 17 Voltage <strong>and</strong> current source2011.06.21 Final Exam (Tue, 6:30 pm)<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh4
P.R. Gray, 5 th Edition1. Models for <strong>IC</strong> Active Devices2. Bipolar, MOS, <strong>and</strong> BiCMOS <strong>IC</strong> Technology3. Single-Transistor <strong>and</strong> Multiple-TransistorAmplifiers4. Current Mirrors, Active Loads, <strong>and</strong> References5. Output Stages6. Operational Amplifiers with Single-EndedOutputs7. Frequency Response of Integrated Circuits8. Feedback9. Frequency Response <strong>and</strong> Stability of FeedbackAmplifiers10. Nonlinear <strong>Analog</strong> Circuits11. Noise in Integrated Circuits12. Fully Differential Operational AmplifiersSyllabus<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- 5Chih-Cheng Hsieh
B. Razavi1. Introduction to <strong>Analog</strong> <strong>Design</strong>2. Basic MOS Device Physics3. Single-Stage Amplifiers4. Differential Amplifiers5. Passive <strong>and</strong> Active Current Mirrors6. Frequency Response7. Noise8. Feedback9. Operational Amplifiers10. Stability <strong>and</strong> Frequency Compensation11. B<strong>and</strong>gap References12. Introduction to Switched-Capacitor Circuits13. Nonlinearity <strong>and</strong> Mismatch14. Oscillators15. Phase-Locked Loops16. Short-Channel Effects <strong>and</strong> Device Models17. CMOS Processing Technology18. Layout <strong>and</strong> PackagingSyllabus<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- 6Chih-Cheng Hsieh
• Homework 20%Grading– The homework will be assigned at every Thur. class, <strong>and</strong> itshould be finished <strong>and</strong> h<strong>and</strong>-in at the following Thur.’s class.Schedule delay is not allowed except it’s with instructor’sapproval.– CAD tools are required for homework.– CAD introduction will be arranged in proper time.• Midterm 20% @ week 9 : 2.5hrs (2011/4/21)• Final Exam 30% @ week 18 : 3hrs (2011/6/21)• Final Project 20% @ week 19 : 10mins / team (2students)• In-Class performance<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh7
<strong>Design</strong> <strong>and</strong> <strong>Analysis</strong>• A circuit analysis <strong>and</strong> design is not "black magic“ !• Circuit analysis– The technique to decompose a large circuit into manageablepieces.– The analysis is based on the simplest, but sufficiently accuratemodels.– Each circuit has one solution.• Circuit design– The art to synthesize circuits that is based on manyexperience of extensive analysis.– One set of specifications has many solutions.– <strong>Design</strong> skills are best acquired through "learning by doing“.• So, we have many practical homework <strong>and</strong> one designproject !!<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh8
Goal & Vision• Touch, Explore, <strong>and</strong> Study <strong>Analog</strong> circuit ….• Then Think, Act <strong>and</strong> like to Be an analog designer. Or…NOT to be an analog designer.• Know how <strong>and</strong> where to dig Knowledge & Skill insidewhen necessary.• Homework & Project are the vehicles to train yourlogistic thinking, design skill <strong>and</strong> team work altitude.• You can study hard by yourself… however…! Interact with me as more as you canis the best way to learn !<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh9
Course Part IWeek Date Descriptions Chapter1 2011.02.22 Introduction, CMOS <strong>and</strong> BJT technologies2 2011.03.01 BJT / MOS Device <strong>and</strong> modeling3 2011.03.08 Single-stage amplifier4 2011.03.15 Single-stage, Multi-stage amplifier5 2011.03.22 Multi-stage amplifier6 2011.03.29 Differential configuration7 2011.04.05 Current mirrors8 2011.04.12 Output stage9 2011.04.19 Feedback I2011.04.21 Midterm (Thur. 6:30 pm) -<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh10
Course Part IIWeek Date Descriptions Chapter10 2011.04.26 Feedback II11 2011.05.03 Frequency response12 2011.05.10 Stability <strong>and</strong> compensation13 2011.05.17 Introduction of op-amp14 2011.05.23 Two-stage op-amp, Differential op-amp15 2011.05.30 <strong>Design</strong> techniques for op-amp I16 2011.06.07 <strong>Design</strong> techniques for op-amp II17 2011.06.14 Voltage <strong>and</strong> current source18 2011.06.21 Final Exam (Tue. 6:30pm)19 2011.06.30 Term Project<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh11
CHAPTER 1Introduction, CMOS TechnologiesSome of the following materials are referred to the course slides of Prof.Huang Po-Chiun @ NTHU<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh12
Outline1. Introduction2. MOS Technologies<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh13
This is <strong>Analog</strong> ??Op-741<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh14
What the $@# is this?<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh15
Find the components you need<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh16
You can make it!<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh17
What is <strong>Analog</strong> ?- Always continuous in amplitude- Either continuous in time (s-domain)or discrete in time (z-domain)<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh18
Where is <strong>Analog</strong> ?Transmissionmediasupplyphysicalinterface Amplification FiltrationDSP Supply Conversion (A/D, D/A)storageaudiovideo Translation(freq, time, volt …)<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh19
Advantages of Digital VLSI• Noise immunity, robustness• Unlimited precision or accuracy• Flexibility, programmability, <strong>and</strong> scalability• Electronic design automation (EDA) tools widelyavailable <strong>and</strong> successful• Benefiting from Moore’s law – “The number oftransistors on a chip doubles every 18 months,”IEDM, 1975– Cost/function drops 29% every year– That’s 30X in 10 yearsRef: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh20
Why Need <strong>Analog</strong>?Paul Gray’s eggshell diagramPhone Lines, Cables(DSL, Cable Modem)E&M Waves(Cellphone, Radio,GPS)<strong>Analog</strong> World(CT, CA)Digital World(DT, DA)Audio( MP3, Hearing Aid)Video(Dig. Camera, LCD TV,TFT Display)Mechanical Transducers(Car/Airplane Sensors,MEMS, Nanopore)Digital Storage(DVD, Hard Disk, Flash)Biochemical Sensors(Hazard detection, DrugDelivery, Lab-on-a-Chip)Ref: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh– 21 –
Challenges for <strong>Analog</strong>• Sensitive to noise – SNR (signal-to-noise ratio)• Subject to device nonlinearities – THD (total harmonicdistortion)• Sensitive to device mismatch <strong>and</strong> process variations• Difficult to design, simulate, layout, test, <strong>and</strong> debug• Inevitable, often limits the overall systemperformance• Scaling scenario outlook– High-speed, low-resolution applications keep benefiting– High SNR design difficult to scale with low supply voltagesRef: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh22
<strong>Analog</strong> Skills• Operation point bias voltage, current ….• Large signal analysis settling, slew rate, distortion ….• Small signal model gain, b<strong>and</strong>width, stability ….• Practical issue in VLSI variation, noise, temperature ….• Cost estimation technology, power, size, yield, package ….Ref: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh23
Example 1 – Mixed-Signal Hearing AidΣΔA/DDSPΣΔD/AH-BridgeDriverAGCDecimationFilter0-50[dB]-100-1500.0010.010.10.5Normalized frequencyRef: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh24
Example 2 – RF TransceiverBCAA/DLNAILOQAAFSCF, G m COP-RCDSPD/APAILOQADesiredchannelBCRF IF or BB BBRef: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh25
SoC – RF Transceiver• Small form factor, high integration, low power, low cost• Economy is the ultimate driving forceRadioDSPADEricsson CH388(Hybrid, 1995)Ericsson Bluetooth(CMOS, 2001)Berkäna GSM/GPRS(CMOS, 2005)Nano-CMOS?Nanotube?Past Present Future<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh– 26 –
System-on-a-ChipSystem integration is the way for the future <strong>IC</strong> development.You need multi-domain knowledge to survive in the SOC era.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh27
<strong>Analog</strong> in VLSI- from ISSCC ‘92<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh28
For Future Nanometer TechnologyIntegration !– Digital has to be treated as <strong>Analog</strong>.– <strong>Analog</strong> needs the help from Digital.– Parasitic effects become dominant.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh29
CoursesMicroelectronicsCommunication / Control / Logic / …VLSI <strong>Design</strong><strong>Analog</strong> <strong>IC</strong>sDigital <strong>IC</strong>sDigital Signal ProcessingSemiconductor DevicesRF/MW Integrated CircuitsCommunication Systems<strong>Design</strong> AutomationSpecial Topics on VLSIsAdvanced <strong>Analog</strong> <strong>IC</strong>sMixed Signal <strong>IC</strong>sCommunication VLSIsVLSI Testing<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh30
<strong>IC</strong> <strong>Design</strong> Related Course Plan31建 議時 程類 別課 名 課 號大 一入 門 課 程邏 輯 設 計EE2280邏 設 實 驗EE2230計 算 機 程 式 語 言EE2310大 二大 三核 心 課 程電 子 學EE2250積 體 電 路 設 計 導 論EE4290類 比 電 路 分 析 與 設 計EE3235實 作 專 題EE3900電 路 學EE2210數 位 電 路 分 析 與 設 計EE3230積 體 電 路 設 計 實 習EE4249訊 號 與 系 統EE3610計 算 機 結 構EE3450電 子 電 路 實 驗EE2270嵌 入 式 系 統 與 實 驗EE2405資 料 結 構EE2410核 心 課 程超 大 型 積 體 電 路 設 計EE5250*超 大 型 積 體 電 路 測 試EE6250積 體 電 路 設 計 自 動 化EE5265* 若 無 修 過 EE4290則 需 修 EE5250大 四 /研 究 所進 階 課 程有 線 通 訊 <strong>IC</strong> 設 計EE5285電 源 管 理 <strong>IC</strong> 設 計EE5275類 比 電 路 設 計ENE5210通 訊 基 頻 <strong>IC</strong> 設 計EE5250內 嵌 式 記 憶 體 電 路EE5220仿 神 經 <strong>IC</strong> 設 計 I,IIEE6260,6261計 算 機 算 數EE5410系 統 晶 片 實 體 設 計EE5253<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh
Outline1. Introduction2. MOS Technlogies<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh32
Content• CMOS Device Background• CMOS Process Key Step• CMOS Process Flow• CMOS Passive Devices<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh33
Generic CMOS This course concentrates on CMOS technology, as it isthe mainstream of modern VLSI.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh34
What is Semi-Conductor Device ?<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh35
First <strong>IC</strong>1952, Royal Radar Establishment of the British Ministry of Defense,Geoffrey W.A. Dummer, No successful implementation !!1958,Jack Kilby,(2000 Nobile prize)Texas Instruments&Robert Noyce,Fairchild Semiconductorhttp://en.wikipedia.org/wiki/Integrated_circuit<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh36
First Planar <strong>IC</strong>• Planar Technology Invented– Made by Robert Noyce of Fairchild in 1959History of VLSI development is reviewed at http://smithsonianchips.si.edu/augarten/index.htm<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh37
Scaling !R. H. Dennard, et. al., IEDM. Dec. 1972.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh38
Mooers’ Law• Intel’s co-founder Gordon Moore notices in 1964– # of transistors per chip doubled every 12 months– Slow down in the 1980s to every 18 monthshttp://video.intel.com/?fr_story=c11efd497dce83c4ca94278fb30c7dfeb01aef16&rf=bm<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh39
Moore’s Prospect<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh40
CPU Transistor # vs. Feature SizeMark Bohr, “The New Era of Scaling in an SoC World”, Plenary session, ISSCC 2009<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh41
Moore’s Law“If GM had kept up with technology like the computerindustry has, we would all be driving $25 cars thatgot 1,000 miles to the gallon…”– Bill Gates, COMDEX keynoteRef: Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh42
Physical Dimension<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh43
• Profile of <strong>IC</strong>What We can do in <strong>IC</strong> ?– 9 metal layers – over the past 30 yearsCuVia 2Via 1Contact(W)M6Via 5M5Via 4M4Via 3M3M2M132nm CMOSSilicon<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh44
CMOS Device Speed<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh45
Integration !GSM/GPRSTI 2006.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh46
Outline• CMOS Device Background• CMOS Process Key Step• CMOS Process Flow• CMOS Passive Devices<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh47
Cleaning• Prior to any high temperature or deposition step– To remove particle, organic films, metals <strong>and</strong> any preexisting“native” oxide films<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh48
Clean Room• US FED STD 209E Cleanroom St<strong>and</strong>ards<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh49
Photolithography• Lithography– Transfer the circuit layout to the wafer– The heart of fabrication technologies• Defines the patterns through mask– Chromium on a transparent glass– With etching processing» Deposited» Ion implantation – change theproperty of silicon• Create patterns in photoresist– A liquid photosensitive chemical thatresists etching processes– Owing to the necessary precision• A slow <strong>and</strong> expensive task<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh50
Photoresist• Photoresist Coating Process– A small amount of photoresist• is dispensed onto the center of the wafer• Is spun to produce the uniform thin film<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh51
Photoresist• Positively Photoresist– Developer dissolves the areas exposed to light quickly• Negative Photoresist– Developer dissolves the areas not exposed to light quickly<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh52
Exposure• Light Sources– ultraviolet (UV) light– Deep ultraviolet (DUV) light– Ion beam– Minimum linewidth <strong>and</strong> exposure wavelength<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh53
Develop• Wash away the photoresist– Whenever light exposed a pattern into the photoresist• Leave the photoresist– Whenever the light was blacked<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh54
Layout• Top View & Profile of MOS Devices<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh55
Mask Layer• Layers<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh56
Etching• Isotropic– Etches in all directions at the same rate• Anisotropic– Achieve the faster etching in one direction than in otherdirections<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh57
Wet Etching• Place the wafer in a chemical liquid– Isotropic• Low precision<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh58
Dry Etching• Plasma Etching– bombarding the wafer with a plasma gas– Anisotropic• High precision<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh59
Oxidation• Object– Gate dielectric– Protective coating in many steps of fabrication<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh60
Oxidation• Silicon Dioxide (SiO2)– Place the silicon in an oxygen gas at 1000°C<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh61
Ion Implementation• Introduce Impurities (Dopants)– To change the electrical properties of the silicon– The most common method for introducing impurities intosilicon wafers• Impurities with an electric charge are accelerated to high energy <strong>and</strong> shotinto the exposed area of the wafer surface<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh62
• AnnealingIon Implementation– Following the ion implementation• A high temperature furnace process is used to anneal out the damage<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh63
• ChannelingIon Implementation– The implant beam is aligned with the crystal axis• The ions penetrate the wafer to a greater depth– The implant beam is tilted by 7-9°<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh64
Chemical Vapor Deposition• A process of depositing films by reacting chemicalvapors to produce a film on a substrate– May be activated by• Heat• RF energy (plasma enhanced, PECVD)• Light (photon induced, PHCVD)– CVD process is used to deposit• Poly <strong>and</strong> single crystal silicon• Dielectric films• Metal films<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh65
Chemical Vapor Deposition• Atmospheric Pressure CVD (APCVD)• Low Pressure CVD (LPCVD)– The most commonly process– More uniformity<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh66
Chemical Vapor Deposition• Plasma Enhanced CVD (PECVD)– Induced by high frequency energy<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh67
Chemical Vapor Deposition• Photon Induced CVD (PHCVD)– Induced by light<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh68
• Sputter ProcessSputter Deposition– Metal films are used in <strong>IC</strong> fabrication• Argon gas is excited by a high energy fieldArgon ionsMetal<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh69
Outline• CMOS Device Background• CMOS Process Key Step• CMOS Process Flow• CMOS Passive Devices<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh70
CMOS Active Device Layout<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh71
An Inverter Example - 0<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh72
An Inverter Example - 1<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh73
An Inverter Example - 2<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh74
An Inverter Example - 3<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh75
An Inverter Example - 4<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh76
An Inverter Example - 5<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh77
An Inverter Example - 6<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh78
An Inverter Example - 7<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh79
An Inverter Example - 8<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh80
An Inverter Example - 9<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh81
Outline• CMOS Device Background• CMOS Process Key Step• CMOS Process Flow• CMOS Passive Devices<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh82
CMOS Active Device Parameter- an example from Boser, UC Berkeley<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh83
Capacitor• Charge storage device– Memory Devices, esp. DRAM– Two boards of semiconductor material as a capacitor• Capacitances– are proportional to the area– are inverse proportional to the distanceldhsymbolC = kε0hldk = dielectric constantε 0 = permittivity<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh84
CMOS Poly-Poly Capacitor‣ Usually for >0.35um or memory technology<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh85
CMOS Metal-Metal Capacitor‣ Usually for
MIM vs. MOM• Metal-Insulator-Metal— Need extra layer— More routing capability• Metal-Oxide-Metal— Free with modern process— More layers : higher density<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh87
CMOS Active Capacitor- from P. Andreani, IEEE JSSC. 2000<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh88
CMOS Passive Capacitor- an example from Boser, UC BerkeleyM-I-M 1000<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh89
Resistor• Polysilicon resistor– is doped on an <strong>IC</strong> chip– Linear• Resistance is determined by length, area, <strong>and</strong> the resistivity of the materialtypeSilicide BlockPolyFOXSilicided PolyP-substratesymbol<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh90
CMOS Resistor LayoutPoly Well Diffusion<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh91
CMOS Passive Resistor- an example from Boser, UC BerkeleyThe resistance of a uniform slab of conducting materialRρ l= =Aρ lt w= RSlwρ : resistivityt : thicknessl : conductor lengthw : conductor widthRS : sheet resistance<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh92
CMOS Passive Inductor<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh93
CMOS Parasitic BJTLateral bipolar pnp:emitter P+,base N-well,collector P-subtrate<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh94
Reference1. Hong-Yi Huang, Mixed Signal <strong>IC</strong> Layout course slides, FuJen CatholicUniversity, 2004.2. B. Boser, “Submicron CMOS Technology for <strong>Analog</strong> <strong>Design</strong>ers”, EECS dept,UC Berkeley, 2003.3. Advanced <strong>Analog</strong> <strong>IC</strong> <strong>Design</strong>, Fall 2009, by Prof. Y. Chiu4. NDL CMOS process introduction.http://www.ndl.org.tw/old/icfab/chinese1/index.htm.<strong>Analog</strong> <strong>IC</strong> <strong>Analysis</strong> <strong>and</strong> <strong>Design</strong> 1- Chih-Cheng Hsieh95
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