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IBM System/7 Functional Characteristics - All about the IBM 1130 ...

IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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STATE CONTROL INSTRUCTIONSLevel Exit (PLEX)0 5 8 15Op code R Zeros0 0 1 1 0 * * 0 0 0 010 0 0 0III! 1 13 0 0 0The processor exits <strong>the</strong> current priority interruption level. If lower-level interruptionsare pending, <strong>the</strong> system remains active and services <strong>the</strong> request on <strong>the</strong> highest pendingpriority level. If no o<strong>the</strong>r interruptions are pending, <strong>the</strong> processor enters <strong>the</strong> wait state.The PLEX instruction does not change <strong>the</strong> carry, overflow, and result indicators.Stop (PSTP)0 5 8 15Op code R Zeros0 0 1 0 0 • 0 0 0 010 0 0 0!III I I 1 1 1 1 12 0 0 0The processor enters <strong>the</strong> stop state, provided <strong>the</strong> <strong>System</strong>/7 console controls switch is in <strong>the</strong>enable position. If this switch is not in <strong>the</strong> enable position, <strong>the</strong> PSTP instruction performsas a no-operation instruction.The PSTP instruction does not change <strong>the</strong> carry, overflow, and result indicators.Supervisor Call (SVC)0 5 8 151 0 0 1 11 11I I I I9 8 ReservedThe summary mask is turned on and a branch is taken via <strong>the</strong> contents of main storagelocation hex 0009. The sequence indicator in <strong>the</strong> processor status word is turned on.No o<strong>the</strong>r indicators are changed. Power/<strong>the</strong>rmal warning interruptions are inhibitedduring this instruction. The contents of <strong>the</strong> instruction address register (IAR) are storedIn <strong>the</strong> address specified by <strong>the</strong> interruption level transfer vector (ILTV) for <strong>the</strong> levelthat is executing. For example, if <strong>the</strong> SVC is issued on level 3, <strong>the</strong> contents of <strong>the</strong> IAR(<strong>the</strong> IAR points to <strong>the</strong> location of <strong>the</strong> SVC) are stored in <strong>the</strong> address specified by <strong>the</strong>contents of main storage location hex 0013.To allow <strong>the</strong> system to respond to as many error conditions as possible, <strong>the</strong> loadprocessor status (PLPS) instruction must be executed after <strong>the</strong> SVC instruction. If not,a machine check or program check condition causes a machine check class interruption.For example, assume that an SVC instruction has been issued and a PLPS has not beenexecuted. If a program check condition occurs or ano<strong>the</strong>r SVC is fetched from mainstorage, <strong>the</strong> processor status word (PSW) is first cleared, <strong>the</strong>n set with <strong>the</strong> appropriateprogram check condition along with control check. If a second SVC is being fetched, aprogram check condition is set. The setting of control check causes a machine check classinterruption if <strong>the</strong> keyswitch is in <strong>the</strong> disable position or <strong>the</strong> check control switch is inProcessor Instructions 4-51

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