IBM System/7 Functional Characteristics - All about the IBM 1130 ...

Executing the OR-to-mask instruction turns off the summary mask function. To do sowithout changing the IMR, the R register must have bits 0-3 set to 0000.Interruption requests are not recognized by the processor during execution of the POMinstruction. After execution of the POM instruction, interruption control is returned tothe mask register, and samples for power/thermal warning class interruptions and priorityinterruptions are resumed.ORing occurs only between corresponding bits in the interruption mask register andthe R register: bit 0 is ORed only with bit 0, bit 1 only with bit 1, and so on. Thefour possible ORing combinations are:Bit Value from Bit Value from Result in InterruptionR Register Interruption Mask Register Mask Register0 0 00 1 11 0 11 1 1Thus, a bit value of 1 will result in the mask register if a corresponding bit positionis set to a value of 1 in the mask register and/or the R register.Example:Register bits 0 to 3Interruption mask register'Result in interruption mask register11010101 (interruptions permitted on levels 1 and 3)1101 (interruptions permitted on levels 0, 1, and 3)Sense Level and Mask (PSLM)0 5 815Op code1 1 1 1 1I IIIRX X XI IModifier0 0 0 Xi1 0 0 1IIIIIIIF 8-F 0 or 1 9The currently active priority level number and the contents of the interruption maskregister are stored in the index register (R), or the accumulator if R=000. The prioritylevel is stored as a binary number in bits 14 and 15 of the register; the interruption maskis stored in bits 0 to 3 exactly as it appears in the interruption mask register. Bits 4 to 13are set to 0's.The PSLM instruction does not change the carry and overflow indicators, or the IMR.The result indicators are changed, however, to reflect the final contents of the R register.The summary mask can be turned on by setting modifier bit 11 in the PSLM instructionto a value of 1. No priority or power/thermal warning interruptions can occur until thesummary mask is turned off. A system reset has somewhat the opposite effect: it sets onall four bits of the interruption mask register so that I/O interruptions can occur on anylevel.