IBM System/7 Functional Characteristics - All about the IBM 1130 ...

INTERRUPTION MASK REGISTER INSTRUCTIONSAND to Mask (PNM)0 5 8 15Op code R Modifier1 0 1 1 0 X X X 0 0 0 0 1 0 0 0 0!III i 1 i 1 l 1 I IB 0-7 0 0The 4-bit interruption mask register is ANDed, bit by bit, with bits 0 to 3 of the indexregister (R), or the accumulator if R=000. This result replaces the contents of the interruptionmask register, where a bit value of 1 means that an interruption is permitted on aparticular priority level. The contents of the R register are not changed; neither are thecarry, overflow, and result indicators.Executing the AND-to-mask instruction turns off the summary mask function. To do sowithout changing the IMR, the R register must have bits 0-3 set to 1111.Interruption requests are not recognized by the processor during execution of the PNMinstruction. After execution of the PNM instruction, interruption control is returned tothe mask register, and samples for power/thermal warning class interruptions and priorityinterruptions are resumed.ANDing occurs only between corresponding bits in the interruption mask registerand the R register: bit 0 is ANDed only with bit 0, bit 1 only with bit 1, and soon. The four possible ANDing combinations are:Bit Value fromR RegisterBit Value fromInterruption Mask Register0 0 00 1 01 0 01 1 1Result in InterruptionMask RegisterThus, a bit value of 1 will result in the mask register only if a corresponding bitposition is set to a value of 1 in both the mask register and the R register.Example:Register bits 0 to 3 1101Interruption mask register 0111 (interruptions permitted on levels 1, 2, and 3)Result in interruption mask register 0101 (interruptions permitted on levels 1 and 3)OR to Mask (POM)0 5 8 15Op codeRModifier1 0 1 1 0 X X X 0 0 0 0 1 0 0 0 1I ill11 11111B 0-7 0 1The 4-bit interruption mask register is ORed, bit by bit, with bits 0 to 3 of the indexregister (R), or the accumulator if R=000. This result replaces the contents of theinterruption mask register, where a bit value of 1 means that an interruption is permittedon a particular priority level. The contents of the R register are not changed; neither arethe carry, overflow, and result indicators.Processor Instructions 4-49