IBM System/7 Functional Characteristics - All about the IBM 1130 ...

Load Processor Status (PLPS)0 5 8 15Op code1 1 1 1 1I I I 1RX X XI IModifier0 0 0 011 0 1 1IIIIIIIF 8-F 0Sixteen bits of processor status information are stored into the index register (oraccumulator if R=000) specified by the R field. Processor status information isrepresented by the values of individual bit positions in the word stored in the register.The bit positions and their meanings follow.Bit Set On Meaning0 Invalid shift count1 Invalid storage address2 Invalid op-code, function, or modifier3 Local storage parity check (XR parity check)4 SDR parity check5 Control check6 I/O check7 Sequence indicator8 Power warning—master unit9 Thermal warning—master unit10 Power warning—remote unit11 Thermal warning—remote unit12-15 (Not used, but are 0's)Bits 0 to 2 are set by program check error conditions, bits 3 to 6 are set by machinecheck error conditions. Bit 7 is set on by execution of a supervisor call (SVC) instructionand remains on until execution of a PLPS instruction. Bits 8 to 11 are set by apower/thermal warning. (For more information on these conditions, see "Class Interruptions"in Chapter 3.)Execution of this instruction resets status indicator bits 0 to 7; indicator bits 8 to 11are reset only when the cause of the warning disappears. None of these status indicatorsare reset by the reset generated by a machine check interruption.The PLPS instruction does not change the carry and overflow indicators. The resultindicators are changed to reflect the contents of the R register.Inspect IAR Backup (P1113)0 5 8 15Op codeModifierand level1 1 1 1 1 X X X 0 0 X X11 1 0 0•••■••■,,•••■■•••■•••••,..■■•••■•••,,••••■■••••■■•,,•■•••,F 8-F 0-3The contents of a backup IAR (associated with a particular priority level) are storedinto the index register (or accumulator if R=000) specified by the R field in theinstruction. The contents of the selected IAR are not changed.