IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Branch Conditional (PBC►0 5 8 9 1631Op code0 1 0 01 1 1010 0 01FConditionsI I 1 1 1 1 1 1 1Address1 1 1 1 1 1 1 1 1 1 1 14 0 X XXX X XOp code0 1 0 01 I 15 8 9 150 XXX1 1FConditionsI I 1 1 1 14 1-7 X XThe branch conditional instruction (PBC) branches to another storage location only ifcertain conditions are not present. These conditions are specified within the PBC instruction.If any one of the specified conditions is present, the PBC instruction does not branch,but continues program execution with the instruction that immediately follows the PBCinstruction.There are two ways of determining the effective address of the storage location that isto be branched to. When R=000, the effective address is in the address field of a longformatPBC instruction. When R does not equal 000, the effective address is contained inthe specified index register (R) and the short-format PBC instruction is used. In either case,if test results cause the branch to be taken, the effective address is loaded into the IAR,and the instruction sequence begins at the effective address.The programmer determines what tests are conducted to decide whether a branch willbe taken. This is accomplished by setting bits on or off in the condition field (bits 8 to 15)of the instruction.The bits and their meanings are shown below:Bit Set On Condition Tested9 Carry and overflow indicators both off10 Zero-result indicator on11 Negative-result indicator on12 Positive-result indicator on13 Even-result indicator on14 Carry indicator off15 Overflow indicator offIf no conditions are tested (all condition field bits are set to 0's), the PBC functions as anunconditional branch. Any combination of testing can be requested.If none of the specified test conditions are present, the branch is taken. If any are present,the branch does not occur and program execution proceeds with the instruction thatimmediately follows the PBC instruction.The branch conditional instruction does not change the carry and result indicators.Testing the overflow indicator with bit 15 always sets the overflow indicator off unlesscondition field bit 8 (overflow-save flag) of the instruction is set on. Testing the overflowindicator with bit 9 does not change the overflow indicator; the overflow-save flag hasno effect.
Example 1:5 8 9 16 31PBC instructionOp code0 1 0 0 0MIR0 0 0IiF0 0Condition0 0 0 0 0 01 1 1 1 1 10 0101 1010 0I IAddress10 110 01 I 101 1011 1 1I 1 1114 0 0 0 0 1 0No testing is requested since all condition field bits are 0's. The effective address is in theaddress field because R=000. Therefore, this instruction is an unconditional branch tostorage location 271.Example 2:PBC instruction (located at 74)O 5 8 9 150Op code1 0 0 0lillR1 0II1F1Condition1 0 0 0 0 0 0!Hill4 5 C 0Carry indicatorOverflow indicator El1AR Index register 50 15 0 15PBC instructionis fetched(Decimal 75)O 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1I 1 1 1 1 1 1 1 1 1 1 1 1 1 1(Decimal 130)0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 01 1 1 1 1 1 1 1 1 1 1 1 1 1 10 0 4 0 0 8 2contenitr:gorfelpPl1/4aRces0 15After PBCinstruction execution. (Decima1130)O 0 0 0 10 0 0 0 1 1 0 0 0 1 0 0 1 01 1 1 1 1 1 1 1 1 1 1 1 1 1 i0 0 8 2The only test requested (bit 9 set on) is that both the carry and overflow indicators areoff. This is not true because the overflow indicator is on. Therefore, this instruction resultsin a branch to location 130, the effective address contained in index register 5.Example 3: In example 2, if the overflow indicator is off, the test requested is true. Inthat case, no branch occurs. Program execution proceeds with the next sequentialinstruction following the short-format branch conditional instruction.Processor Instructions 4-35
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GA34-0003-7File No. S7-00IBM System
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ContentsPrefaceChapter 1. Introduct
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Flagging 15-26Track Initialization
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PrefaceThis reference manual is a s
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IntroductionCHAPTER CONTENTSSystem/
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Figure 1-1. IBM 5028 Operator Stati
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• One or two analog output points
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Power Failure and Thermal WarningPo
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IBM 5010 Processor ModuleCHAPTER CO
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StorageProcessorAACycleSteal/ Featu
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The processor does not recognize in
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DATA FORMATSInput/output data can b
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The absolute form can be obtained i
Page 29 and 30: Accumulators (ACC 0 to ACC 3)Page o
Page 31 and 32: Overflow IndicatorThe overflow indi
Page 33 and 34: System/7 InterruptionsCHAPTER CONTE
Page 35 and 36: Level 1interruptionprocessing'.ros
Page 37 and 38: Interruption Mask Register and Summ
Page 39 and 40: Page of GA34-0003-6,-7As Updated Au
Page 41 and 42: The accumulator associated with the
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Page 45 and 46: The summary mask isturned on; sampl
Page 47 and 48: Processor InstructionsCHAPTER CONTE
Page 49 and 50: InstructionMnemonic'OperationcodeLo
Page 51 and 52: ' rrrI !Mil,. '11111E1 luluINSTRUCT
Page 54 and 55: "" ',Pli iI 1114111111111111 111111
Page 56 and 57: Load Immediate (PLI)0 5 8 15Op code
Page 58 and 59: Store Accumulator (PST)0 5 8 15Op c
Page 60 and 61: vow wow. •1•01111111111111111
Page 62 and 63: NMI INNI 1111=111111 IM11111■1111
Page 64 and 65: 11111 !III VIII I 1101 1,411111111,
Page 66 and 67: I i 1111111'1Np■I0111m PIP ,ili11
Page 68 and 69: Example:Word in accumulator 0110 11
Page 70 and 71: Exclusive ORing occurs only between
Page 72 and 73: Shift Left Circular (PSLC)0 5 8 11
Page 74 and 75: Shift Right Arithmetic (PSRA)0 5 8
Page 76 and 77: Example:PB instruction(R = 110 spec
Page 78 and 79: Branch and Link Long (PBALL)0 5 8 1
Page 82 and 83: Branch and Unmask Long (BUL) (5010
Page 84 and 85: Skip Conditional (PSKC)0 5 8 9 15Op
Page 86 and 87: Example:0 5 8 15PAS instruction(loc
Page 88 and 89: Load from Register (PLR)0 5 8 15Op
Page 90 and 91: Load Processor Status (PLPS)0 5 8 1
Page 92 and 93: Write IAR Backup (WIB) (5010 Proces
Page 94 and 95: Store Indicators (STI) (5010 Proces
Page 96 and 97: Executing the OR-to-mask instructio
Page 98 and 99: the process position. If the system
Page 100 and 101: Read Protect Key (RPK)0 5 8 11 16 2
Page 102 and 103: Module address field:Module address
Page 104 and 105: 11111E111111111 M11111111•11111 1
Page 106 and 107: 1111111111111111111111■11•11111
Page 108 and 109: Page of GA34-0003-6, -7As Updated A
Page 110 and 111: Sixteen bits of additional module i
Page 112 and 113: 1 REG 1---LEVEL0 10 0 2 1 20 0 0 03
Page 114 and 115: CTL CHK (Control Check) LightThis l
Page 116 and 117: 1111■111111,11,11N I IIIADDRESS L
Page 118 and 119: CHECK CONTROL SwitchThis three-posi
Page 120 and 121: START KeyPressing the start key cau
Page 122 and 123: The processor module contains two 1
Page 124 and 125: 6-4 GA34-0003II I 1 1 III 111 1111
Page 126 and 127: .11.1111111.111 MP I 111.10114P III
Page 128 and 129: 1111 Minn. 11111111R !VW IMF" !PFLI
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The ACCA must be selected in order
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111.1111 111111 N uData and control
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I II III• 1111111111111111 1•11
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Significant Bits Meaning7* Data set
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I■ 0=11 1111111 MEM11 1111111111
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". — •• 11•111•MI !IF lim
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V IIF 1,1 NM IICONTROL CHARACTERS A
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Character SynchronizationCharacter
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Bit 1-Reserved.Bit 2-Transmit Opera
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Page of GA34-0003-6, -7As Updated A
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1,114plilloi 1110 1111 1111.11 VI P
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1 1 - 1111=111111111 111M 1111 111
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The 5028 Operator Station (Figure 9
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Thickness Paper - .004 + .0003" (0,
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Character bit position 84 Tape move
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If the operator station motor is no
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Feed Tape and Print0 5 8 11 16 20 2
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Read 1SW0 5 8 11 16 20 26 31Op code
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The 5014 Analog Input Module Model
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Convert Analog Input with External
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Read ISW0 5 8 11 16 20 26 31Op code
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10-8 GA34-0003
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11111811111111.1.1.14.111.1111I II
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" 11, 141MINMIIIIF I WPM P IP !! 11
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Read and Convert ADC0 5 8 11 16 20
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Device Status Word (DSW): The 16 bi
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1411111111,1111111111n 111The 5014
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Convert Analog Input with External
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12-6 GA34-0003
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The 5012 Multifunction Module Model
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MODULE DEVICE ADDRESSESANALOG INPUT
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The range bits (RRR) in the control
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H1111111111111 1111.111111HIVRead A
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I/0 CommandsThe prepare I/O and hal
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Data stored in the register can hav
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If a particular amplifier gain was
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' 14 111•141111111111111011114111
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Read Digital Input Reference Regist
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Digital Input Groups Without Proces
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CIA ^iN1i Ma IIl AMINNNP u 11.!..11
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Write Analog Output Holding Registe
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1111111■11111111101=11111.1111111
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=111111111111111111 1 11 1 11111111
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DataThe data byte contains either d
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Read CommandsAll read commands are
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Write Null Acknowledge: This code (
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Area Station Local I/O Guidance Cha
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2791/2793 Adapter Critical timingIn
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BeginDSC* 05Write(AS enters data mo
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oww1111111111111111111111111,1,, V
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Bit 15 in the R register can be set
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The 5013 Digital I/O Module Model A
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The prepare I/O command is used as
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Read Digital Input RegisterO 5 8 11
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Set Digital Input Interrupt Control
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DIGITAL OUTPUT CONTROLThe Digital O
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The 2792 Remote Communications Cont
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Data TransmissionInformation is tra
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The functions of the five bytes in
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Code nameHexBit patternResponse Com
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Read End Acknowledge: This code (he
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Begin Diagnostic: This code (hexade
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Command SequencesThe 2790 Control m
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An area station requiring service l
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Set Diagnostic Mode0 5 8 11 16 20 2
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14-32 GA34-0003
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FUNCTIONAL DESCRIPTIONThe IBM 5022
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FILE ORGANIZATIONEach surface of ea
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Sector Identifier FormatEach identi
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If fewer than 128 words are to be t
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When the IPL operation starts, the
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Recalibrate Operation: A recalibrat
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1111 11 I 111111111111WRead Initial
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If an error is detected during a da
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None of the data read is transferre
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Error and Status ConditionsErrors d
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Significant Bits Meaning5* No recor
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Significant Bits Meaning3 Seek chec
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FLAGGINGThe condition of a track su
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Track Initialization ProceduresThe
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Bit 5—No Record FoundIt should be
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15-32 GA34-0003
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I III 1111111111111111111111111111
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Interruptions to System/7The progra
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Initiate Read0 16 21 24 31111111Add
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Device Status Word (DSW): The 16-bi
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16-10 GA34-0003
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The IBM 5024 I/O Attachment Enclosu
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III 1111•1111111111•1111111 III
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11111 1 11•1111111111111111111111
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Reset 5024The reset 5024 resets the
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2502 Card Reader Translate TableA 2
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I/O Transfer BlockThe address of th
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Status Word 1.0 152502 status buffe
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Status Word 2.0 15Status word 1% St
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1 1 111111111111111111111111111•1
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IMP P 1111,1111.11,11311111 I MP 11
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11 11 1111111111 1 1111111111111111
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algaaaagIrlug",',/"'", BeltPosition
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• Disable Attention Interrupt 110
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Status Word 1.0 15aStatus word 1•
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Status Word 2.15Status word 1N+1Res
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Interrupt PresentationThe printer a
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17-30 GA34-0003
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Add immediateMnemonicExecutiontime
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Alter storage key (provided only wi
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BranchMnemonicExecutiont i me (ns)O
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Branch conditionalMnemonicExecution
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Exclusive OR registertMnemonicExecu
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Level exitMnemonicExecutiontime (ns
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Load immediateMnemonicExecutiontime
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OR registerMnemonicExecutiontime (n
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Read protect key (provided only wit
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1111■11111■111111111 1 11111111
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StopMnemonicExecutiontime Ins)Op co
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SubtractMnemonicExecutiontime (ns)O
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A-26 GA34-0003
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PIO instruction Function ModifierDe
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1111111■111111PIO instruction Fun
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Valid responses to 2790 read comman
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Interrupt status wordsDevice0 1 2 3
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Device status word (2502, 5024 with
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11.1 11111 11110•11111111111.1111
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5028ConsoleShift/ 5028BSCAACCAContr
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5028ConsoleShift/ 5028BSCAACCAContr
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triNtitTIBitRanges and bit values (
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.••■• III II III 11111.•
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E-6 GA34-0003
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Verifydata beforewrite analogoutput
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Prepare I/OSet referenceregisterYes
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F-6 GA34-0003IIII•1111■•■
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G-2 GA34-0003
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analog signal resolution (continued
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cycle steal feature data flow 2-3cy
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forced interruption control, digita
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initial program load (IPL) to Syste
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111111•1111111111■ IllO (OR) in
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ead, 5022 Disk Storage Module (cont
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11111111111111111■1 1111111 11111
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X-16 GA34-0003
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GA34-0003-7Your comments, please ..
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I 111111111111111.1 I MEM II 1 1111
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