IBM System/7 Functional Characteristics - All about the IBM 1130 ...

More documents

Recommendations

Info

Machine CheckMachine check interruptions occur when processor error checking circuits detect a machinemalfunction. Malfunctions can be caused by:1. A parity error in an index register.2. A parity error encountered by the processor attempting to access main storage_3. More than one type of machine cycle requested or taken simultaneously.4. More than one interruption level being executed simultaneously, or no level isactive and the processor is taking machine cycles.5. An I/O hardware error occurring on the internal interface.Note: A machine check error can result from programming if a storage location or anindex register is used by the program and the location or register was not loadedwith an initial value after the system was powered on. A machine check can also resultfrom a software error when a program check is encountered between the execution ofa supervisor call instruction and a load processor status instruction, or when anothersupervisor call instruction is issued.Operator console lights indicate the cause of a machine check when the processor isin the stop state. Only one machine check can occur at any one time in the system.When a machine check interruption occurs, all I/O devices and pending interruptionrequests are reset. The address of the instruction being executed when the error occurredis saved automatically in storage location hex D. The contents of storage location hex B,which contains the starting address of the machine check servicing routine, are then automaticallyloaded into the IAR and the servicing routine is given control. (Refer to"Reserved Storage Locations" in this chapter.)Program CheckProgram check interruptions occur when the processor detects a machine instruction thatis invalid for one of the following reasons:1. Invalid operation code (an invalid instruction for the System/7 processor).2. Invalid modifier field contents in instructions with operation code of 11111. (Onprocessor module model E, this condition causes a no-operation and does not resultin a program check.)3. Invalid address (a main-storage address that exceeds the limits of the storageinstalled in the system).4. Invalid function field (000) in an execute I/O instruction (processor module modelsA and B only).5. Invalid shift count value in shift instructions.6. A cycle steal I/O instruction has been issued and there is no cycle steal featureinstalled in the processor.7. The processor has attempted to alter a storage protected area without the properkey (processor module model E only).When the machine is in the stop state, operator console lights indicate the causeof a program check.
Page of GA34-0003-6, -7As Updated August 20,1976By TNL GN34-0340When a program check interruption occurs on one of the four priority interruptionlevels, the address of the instruction being executed when the program check was detectedis saved automatically in the first word of the appropriate level table. The program checkmay be due to an invalid instruction, or an invalid address generated by an instruction. Ifan invalid instruction is detected, the first word of the appropriate level table (OIA) containsthe instruction address. If an invalid address is detected, the OIA normally containsthe address of the instruction that generated the invalid address. (There is one exception tothis. If a higher level priority interruption occurs during a branch to an invalid address, andthe interrupt is accepted immediately following the branch instruction, then the invalidaddress is not used or checked until control is returned to the lower priority level. Underthese circumstances, the OIA contains the address of the PLEX instruction that releasedcontrol from the higher priority level.) The contents of storage location 9, which containsthe starting addreE of the program check servicing routine, are then automatically loadedinto the IAR and the servicing routine is given control. (Refer to "Reserved Storage Locations"in this chapter.)Power/Thermal WarningA power/thermal warning interruption occurs when the system senses a condition caused byvoltage or temperature changes that border on the operating limits of the system. (Referto "Power Failure and Thermal Warning" in Chapter 1.) Power/thermal warning classinterruptions are controlled by the summary mask. If the summary mask is on, the classinterruption is inhibited.Power/thermal warning interruptions are also affected by the settings of the consoleswitches as shown in Figure 3-5.When a voltage or temperature condition causes a power/thermal warning interruption,the IAR contents (address of the next instruction in the interrupted program) are savedautomatically in storage location hex C. The contents of storage location hex A, whichcontains the starting address of the power/thermal warning servicing routine, are thenautomatically loaded into the IAR and the servicing routine is given control. (Refer to"Reserved Storage Locations" in this chapter.)System/7 Interruptions 3-11
Page 3 and 4: GA34-0003-7File No. S7-00IBM System
Page 5 and 6: ContentsPrefaceChapter 1. Introduct
Page 7 and 8: Flagging 15-26Track Initialization
Page 9 and 10: PrefaceThis reference manual is a s
Page 11 and 12: IntroductionCHAPTER CONTENTSSystem/
Page 13 and 14: Figure 1-1. IBM 5028 Operator Stati
Page 15 and 16: • One or two analog output points
Page 17 and 18: Power Failure and Thermal WarningPo
Page 19 and 20: IBM 5010 Processor ModuleCHAPTER CO
Page 21 and 22: StorageProcessorAACycleSteal/ Featu
Page 23 and 24: The processor does not recognize in
Page 25 and 26: DATA FORMATSInput/output data can b
Page 27 and 28: The absolute form can be obtained i
Page 29 and 30: Accumulators (ACC 0 to ACC 3)Page o
Page 31 and 32: Overflow IndicatorThe overflow indi
Page 33 and 34: System/7 InterruptionsCHAPTER CONTE
Page 35 and 36: Level 1interruptionprocessing'.ros
Page 37 and 38: Interruption Mask Register and Summ
Page 39 and 40: Page of GA34-0003-6,-7As Updated Au
Page 41: The accumulator associated with the
Page 45 and 46: The summary mask isturned on; sampl
Page 47 and 48: Processor InstructionsCHAPTER CONTE
Page 49 and 50: InstructionMnemonic'OperationcodeLo
Page 51 and 52: ' rrrI !Mil,. '11111E1 luluINSTRUCT
Page 54 and 55: "" ',Pli iI 1114111111111111 111111
Page 56 and 57: Load Immediate (PLI)0 5 8 15Op code
Page 58 and 59: Store Accumulator (PST)0 5 8 15Op c
Page 60 and 61: vow wow. •1•01111111111111111
Page 62 and 63: NMI INNI 1111=111111 IM11111■1111
Page 64 and 65: 11111 !III VIII I 1101 1,411111111,
Page 66 and 67: I i 1111111'1Np■I0111m PIP ,ili11
Page 68 and 69: Example:Word in accumulator 0110 11
Page 70 and 71: Exclusive ORing occurs only between
Page 72 and 73: Shift Left Circular (PSLC)0 5 8 11
Page 74 and 75: Shift Right Arithmetic (PSRA)0 5 8
Page 76 and 77: Example:PB instruction(R = 110 spec
Page 78 and 79: Branch and Link Long (PBALL)0 5 8 1
Page 80 and 81: Branch Conditional (PBC►0 5 8 9 1
Page 82 and 83: Branch and Unmask Long (BUL) (5010
Page 84 and 85: Skip Conditional (PSKC)0 5 8 9 15Op
Page 86 and 87: Example:0 5 8 15PAS instruction(loc
Page 88 and 89: Load from Register (PLR)0 5 8 15Op
Page 90 and 91: Load Processor Status (PLPS)0 5 8 1
Page 92 and 93:
Write IAR Backup (WIB) (5010 Proces
Page 94 and 95:
Store Indicators (STI) (5010 Proces
Page 96 and 97:
Executing the OR-to-mask instructio
Page 98 and 99:
the process position. If the system
Page 100 and 101:
Read Protect Key (RPK)0 5 8 11 16 2
Page 102 and 103:
Module address field:Module address
Page 104 and 105:
11111E111111111 M11111111•11111 1
Page 106 and 107:
1111111111111111111111■11•11111
Page 108 and 109:
Page of GA34-0003-6, -7As Updated A
Page 110 and 111:
Sixteen bits of additional module i
Page 112 and 113:
1 REG 1---LEVEL0 10 0 2 1 20 0 0 03
Page 114 and 115:
CTL CHK (Control Check) LightThis l
Page 116 and 117:
1111■111111,11,11N I IIIADDRESS L
Page 118 and 119:
CHECK CONTROL SwitchThis three-posi
Page 120 and 121:
START KeyPressing the start key cau
Page 122 and 123:
The processor module contains two 1
Page 124 and 125:
6-4 GA34-0003II I 1 1 III 111 1111
Page 126 and 127:
.11.1111111.111 MP I 111.10114P III
Page 128 and 129:
1111 Minn. 11111111R !VW IMF" !PFLI
Page 130 and 131:
The ACCA must be selected in order
Page 132 and 133:
111.1111 111111 N uData and control
Page 134 and 135:
I II III• 1111111111111111 1•11
Page 136 and 137:
Significant Bits Meaning7* Data set
Page 138 and 139:
I■ 0=11 1111111 MEM11 1111111111
Page 140 and 141:
". — •• 11•111•MI !IF lim
Page 142 and 143:
V IIF 1,1 NM IICONTROL CHARACTERS A
Page 144 and 145:
Character SynchronizationCharacter
Page 146 and 147:
Bit 1-Reserved.Bit 2-Transmit Opera
Page 148 and 149:
Page 150 and 151:
1,114plilloi 1110 1111 1111.11 VI P
Page 152 and 153:
Page 154 and 155:
1 1 - 1111=111111111 111M 1111 111
Page 156 and 157:
The 5028 Operator Station (Figure 9
Page 158 and 159:
Thickness Paper - .004 + .0003" (0,
Page 160 and 161:
Character bit position 84 Tape move
Page 162 and 163:
If the operator station motor is no
Page 164 and 165:
Feed Tape and Print0 5 8 11 16 20 2
Page 166 and 167:
Read 1SW0 5 8 11 16 20 26 31Op code
Page 168 and 169:
The 5014 Analog Input Module Model
Page 170 and 171:
Convert Analog Input with External
Page 172 and 173:
Read ISW0 5 8 11 16 20 26 31Op code
Page 174 and 175:
10-8 GA34-0003
Page 176 and 177:
11111811111111.1.1.14.111.1111I II
Page 178 and 179:
" 11, 141MINMIIIIF I WPM P IP !! 11
Page 180 and 181:
Read and Convert ADC0 5 8 11 16 20
Page 182 and 183:
Device Status Word (DSW): The 16 bi
Page 184 and 185:
1411111111,1111111111n 111The 5014
Page 186 and 187:
Convert Analog Input with External
Page 188 and 189:
12-6 GA34-0003
Page 190 and 191:
The 5012 Multifunction Module Model
Page 192 and 193:
MODULE DEVICE ADDRESSESANALOG INPUT
Page 194 and 195:
The range bits (RRR) in the control
Page 196 and 197:
H1111111111111 1111.111111HIVRead A
Page 198 and 199:
I/0 CommandsThe prepare I/O and hal
Page 200 and 201:
Data stored in the register can hav
Page 202 and 203:
If a particular amplifier gain was
Page 204 and 205:
' 14 111•141111111111111011114111
Page 206 and 207:
Read Digital Input Reference Regist
Page 208 and 209:
Digital Input Groups Without Proces
Page 210 and 211:
CIA ^iN1i Ma IIl AMINNNP u 11.!..11
Page 212 and 213:
Write Analog Output Holding Registe
Page 214 and 215:
1111111■11111111101=11111.1111111
Page 216 and 217:
=111111111111111111 1 11 1 11111111
Page 218 and 219:
DataThe data byte contains either d
Page 220 and 221:
Read CommandsAll read commands are
Page 222 and 223:
Write Null Acknowledge: This code (
Page 224 and 225:
Area Station Local I/O Guidance Cha
Page 226 and 227:
2791/2793 Adapter Critical timingIn
Page 228 and 229:
BeginDSC* 05Write(AS enters data mo
Page 230 and 231:
oww1111111111111111111111111,1,, V
Page 232 and 233:
Bit 15 in the R register can be set
Page 234 and 235:
The 5013 Digital I/O Module Model A
Page 236 and 237:
The prepare I/O command is used as
Page 238 and 239:
Read Digital Input RegisterO 5 8 11
Page 240 and 241:
Set Digital Input Interrupt Control
Page 242 and 243:
DIGITAL OUTPUT CONTROLThe Digital O
Page 244 and 245:
The 2792 Remote Communications Cont
Page 246 and 247:
Data TransmissionInformation is tra
Page 248 and 249:
The functions of the five bytes in
Page 250 and 251:
Code nameHexBit patternResponse Com
Page 252 and 253:
Read End Acknowledge: This code (he
Page 254 and 255:
Begin Diagnostic: This code (hexade
Page 256 and 257:
Page 258 and 259:
Command SequencesThe 2790 Control m
Page 260 and 261:
An area station requiring service l
Page 262 and 263:
Set Diagnostic Mode0 5 8 11 16 20 2
Page 264 and 265:
14-32 GA34-0003
Page 266 and 267:
FUNCTIONAL DESCRIPTIONThe IBM 5022
Page 268 and 269:
FILE ORGANIZATIONEach surface of ea
Page 270 and 271:
Sector Identifier FormatEach identi
Page 272 and 273:
If fewer than 128 words are to be t
Page 274 and 275:
When the IPL operation starts, the
Page 276 and 277:
Recalibrate Operation: A recalibrat
Page 278 and 279:
1111 11 I 111111111111WRead Initial
Page 280 and 281:
If an error is detected during a da
Page 282 and 283:
None of the data read is transferre
Page 284 and 285:
Error and Status ConditionsErrors d
Page 286 and 287:
Significant Bits Meaning5* No recor
Page 288 and 289:
Significant Bits Meaning3 Seek chec
Page 290 and 291:
FLAGGINGThe condition of a track su
Page 292 and 293:
Track Initialization ProceduresThe
Page 294 and 295:
Bit 5—No Record FoundIt should be
Page 296 and 297:
15-32 GA34-0003
Page 298 and 299:
I III 1111111111111111111111111111
Page 300 and 301:
Interruptions to System/7The progra
Page 302 and 303:
Initiate Read0 16 21 24 31111111Add
Page 304 and 305:
Device Status Word (DSW): The 16-bi
Page 306 and 307:
16-10 GA34-0003
Page 308 and 309:
The IBM 5024 I/O Attachment Enclosu
Page 310 and 311:
III 1111•1111111111•1111111 III
Page 312 and 313:
11111 1 11•1111111111111111111111
Page 314 and 315:
Reset 5024The reset 5024 resets the
Page 316 and 317:
2502 Card Reader Translate TableA 2
Page 318 and 319:
I/O Transfer BlockThe address of th
Page 320 and 321:
Status Word 1.0 152502 status buffe
Page 322 and 323:
Status Word 2.0 15Status word 1% St
Page 324 and 325:
1 1 111111111111111111111111111•1
Page 326 and 327:
IMP P 1111,1111.11,11311111 I MP 11
Page 328 and 329:
11 11 1111111111 1 1111111111111111
Page 330 and 331:
algaaaagIrlug",',/"'", BeltPosition
Page 332 and 333:
• Disable Attention Interrupt 110
Page 334 and 335:
Status Word 1.0 15aStatus word 1•
Page 336 and 337:
Status Word 2.15Status word 1N+1Res
Page 338 and 339:
Interrupt PresentationThe printer a
Page 340 and 341:
17-30 GA34-0003
Page 342 and 343:
Add immediateMnemonicExecutiontime
Page 344 and 345:
Alter storage key (provided only wi
Page 346 and 347:
BranchMnemonicExecutiont i me (ns)O
Page 348 and 349:
Branch conditionalMnemonicExecution
Page 350 and 351:
Exclusive OR registertMnemonicExecu
Page 352 and 353:
Level exitMnemonicExecutiontime (ns
Page 354 and 355:
Load immediateMnemonicExecutiontime
Page 356 and 357:
OR registerMnemonicExecutiontime (n
Page 358 and 359:
Read protect key (provided only wit
Page 360 and 361:
1111■11111■111111111 1 11111111
Page 362 and 363:
StopMnemonicExecutiontime Ins)Op co
Page 364 and 365:
SubtractMnemonicExecutiontime (ns)O
Page 366 and 367:
A-26 GA34-0003
Page 368 and 369:
PIO instruction Function ModifierDe
Page 370 and 371:
1111111■111111PIO instruction Fun
Page 372 and 373:
Valid responses to 2790 read comman
Page 374 and 375:
Interrupt status wordsDevice0 1 2 3
Page 376 and 377:
Device status word (2502, 5024 with
Page 378 and 379:
11.1 11111 11110•11111111111.1111
Page 380 and 381:
5028ConsoleShift/ 5028BSCAACCAContr
Page 382 and 383:
5028ConsoleShift/ 5028BSCAACCAContr
Page 384 and 385:
triNtitTIBitRanges and bit values (
Page 386 and 387:
.••■• III II III 11111.•
Page 388 and 389:
E-6 GA34-0003
Page 390 and 391:
Verifydata beforewrite analogoutput
Page 392 and 393:
Prepare I/OSet referenceregisterYes
Page 394 and 395:
F-6 GA34-0003IIII•1111■•■
Page 396 and 397:
G-2 GA34-0003
Page 398 and 399:
analog signal resolution (continued
Page 400 and 401:
cycle steal feature data flow 2-3cy
Page 402 and 403:
forced interruption control, digita
Page 404 and 405:
initial program load (IPL) to Syste
Page 406 and 407:
111111•1111111111■ IllO (OR) in
Page 408 and 409:
ead, 5022 Disk Storage Module (cont
Page 410 and 411:
11111111111111111■1 1111111 11111
Page 412:
X-16 GA34-0003
Page 416 and 417:
GA34-0003-7Your comments, please ..
Page 419 and 420:
I 111111111111111.1 I MEM II 1 1111
show all

IBM System/7 Functional Characteristics - All about the IBM 1130 ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?