IBM System/7 Functional Characteristics - All about the IBM 1130 ...

HOST ATTACHMENT INTERRUPTIONSInterruptions to 1130The 1130 host attachment presents interruptions to the 1130 on its interruption level 3.Interruption requests are made to the 1130 under any of the following conditions:1. The DSW attention bit is set on because a System/7 set interrupt command isdirected to the 1130 (if the interruption controls do not inhibit the interruptionrequest).2. The DSW operation-end bit is set on. (The count=0 DSW bit, the power/thermalwarning bit, or an error bit is also on for this interruption request.)3. The DSW power or thermal warning bit is set on by the corresponding condition(if the interruption controls do not inhibit the interruption request). The DSWready bit remains on until the power actually fails. If a data transfer operation isin progress when the power/thermal warning bit comes on, the operation-end bitis also set on, requesting an interruption to the 1130.The interruption that occurs at the operation-end time of a data transfer can be directedto the System/7 as well as to the 1130. However, if an error is detected during the datatransfer, the operation is terminated and the interruption is directed to the 1130 only(count=0 DSW bit may or may not be set on).When the System/7 directs a set interrupt command to the 1130 attachment, the DSWattention bit (bit 0) is set on unless it is already on. If already on, condition code 2 isreturned to the System/7. If the 1130 attachment is busy,'the attention bit is set on andindicated to the 1130 at the time an operation-end interrupt occurs for the operation inprogress. If the 1130 attachment is not busy, the attention bit is set on and an interruptionrequest is made to the 1130 on its priority level 3 unless attention interruptions areinhibited by the host attachment interruption controls.The host attachment interruption controls, which permit or prevent attention andpower/thermal interruptions to the 1130, are determined by the setting of modifier fieldbits 28 to 30 in an 1130 IOCC. Modifier bits 28 and 29 are the basic interruption control;bit 30 is a temporary interruption control. Attention and power/thermal interruptions arepermitted only if the basic status is "permit" and there is no temporary "prevent." If thebasic status prevents attention and power/thermal interruptions, these interruptions arenot permitted again until another control IOCC that alters the basic interruption controlstatus is executed to permit the interruptions.If interruptions are temporarily prevented as directed by bit 30 in a control IOCC, theyare not permitted again until one of the following occurs:1. The DSW is reset.2. Another control IOCC is executed with bit 30 changing the previous temporarystatus.3. An initiate read or initiate write IOCC is executed.Following any of these events, the 1130 host attachment returns to the basic interruptioncontrol status.Attention and power/thermal interruptions to the 1130 are also prevented by either aSystem/7 power-on reset or an 1130 Storage Access Channel reset. These interruptions arenot permitted again until a control IOCC is executed to establish a basic interruptioncontrol status.1130 Host Attachment 16-3