IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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I III 1111111111111111111111111111 ^"'The IBM 5010 Processor Module Model Bxx attaches the System/7 directly to an IBM1130 Computing System via the 1130 Storage Access Channel (SAC) and the 1130 hostattachment in the System/7. The 1130 host attachment in the processor module permitsdirect, two-way storage-to-storage communication and information transfer between thetwo systems. The 1130 host attachment precludes using the System/7 as a satelliteprocessor by means of the Asynchronous Communications Control Attachment or theBinary Synchronous Communications Adapter.FUNCTIONAL DESCRIPTIONThe 1130 host attachment can be connected to either the 1130 SAC or the 1130 SAC II.The host attachment transfers data or instructions at the 1130 storage speed (454 kHz onthe 2.2-microsecond 1130 or 277 kHz on the 3.6-microsecond 1130). Although theattachment requests 1130 cycles so quickly that it may prevent instruction executionin the 1130 processor (except for interruption level 0 or 1), the System/7 storage speedpermits execution of System/7 instructions during a data transfer.Interruption level 0 or 1 instructions are executed in the 1130 during a data transferbecause the System/7 interrupts the 1130 on interrupt level 3 and, consequently, theSystem/7 must obey the inhibit-cycle-steal-request line from the 1130 during higherpriorityinterruptions. For further details, refer to the manual 1131 Central ProcessingUnit and 1133 Multiplex Control Enclosure Storage Access Channel—Original EquipmentManufacturer's Information, Order No. GA26-3645.Use of System/7 storage by the two systems requires both machine and program controlsto resolve conflicts for access to System/7 storage. The System/7 has an interruptionmechanism that enables either system to alert the other for service. To determine thenature of the service required, programming must maintain current control parametersin a System/7 storage area.All data transfers are initiated by the 1130, and all end or error conditions are signaledto the 1130 by means of interruptions. No direct communication exists between the 1130and the System/7 I/O modules; data transfers are strictly storage-to-storage.Although no provision is made for parity within the 1130 SAC, the 1130 host attachmentgenerates the necessary parity for data destined for System/7 storage.A host attachment switch located on the System/7 console controls the connectionbetween the System/7 and the 1130. When in the disable position, interrupt and cyclestealrequests cannot go to the 1130, all 1130 instructions are ignored, and conditioncode 3 is returned if a System/7 set interrupt command is addressed to the host attachment.When the switch is in the enable or enable and IPL position, the 1130 and System/7 cancommunicate through the SAC in a normal manner. The 1130 attachment is reset whenthe 1130 console reset key is depressed or if the System/7 console host attachment switchis moved from the enable or the enable and IPL position. IPL from the 1130 is describedlater in this chapter under "Electronic Initial Program Load (EIPL)."16-2 GA34-0003
HOST ATTACHMENT INTERRUPTIONSInterruptions to 1130The 1130 host attachment presents interruptions to the 1130 on its interruption level 3.Interruption requests are made to the 1130 under any of the following conditions:1. The DSW attention bit is set on because a System/7 set interrupt command isdirected to the 1130 (if the interruption controls do not inhibit the interruptionrequest).2. The DSW operation-end bit is set on. (The count=0 DSW bit, the power/thermalwarning bit, or an error bit is also on for this interruption request.)3. The DSW power or thermal warning bit is set on by the corresponding condition(if the interruption controls do not inhibit the interruption request). The DSWready bit remains on until the power actually fails. If a data transfer operation isin progress when the power/thermal warning bit comes on, the operation-end bitis also set on, requesting an interruption to the 1130.The interruption that occurs at the operation-end time of a data transfer can be directedto the System/7 as well as to the 1130. However, if an error is detected during the datatransfer, the operation is terminated and the interruption is directed to the 1130 only(count=0 DSW bit may or may not be set on).When the System/7 directs a set interrupt command to the 1130 attachment, the DSWattention bit (bit 0) is set on unless it is already on. If already on, condition code 2 isreturned to the System/7. If the 1130 attachment is busy,'the attention bit is set on andindicated to the 1130 at the time an operation-end interrupt occurs for the operation inprogress. If the 1130 attachment is not busy, the attention bit is set on and an interruptionrequest is made to the 1130 on its priority level 3 unless attention interruptions areinhibited by the host attachment interruption controls.The host attachment interruption controls, which permit or prevent attention andpower/thermal interruptions to the 1130, are determined by the setting of modifier fieldbits 28 to 30 in an 1130 IOCC. Modifier bits 28 and 29 are the basic interruption control;bit 30 is a temporary interruption control. Attention and power/thermal interruptions arepermitted only if the basic status is "permit" and there is no temporary "prevent." If thebasic status prevents attention and power/thermal interruptions, these interruptions arenot permitted again until another control IOCC that alters the basic interruption controlstatus is executed to permit the interruptions.If interruptions are temporarily prevented as directed by bit 30 in a control IOCC, theyare not permitted again until one of the following occurs:1. The DSW is reset.2. Another control IOCC is executed with bit 30 changing the previous temporarystatus.3. An initiate read or initiate write IOCC is executed.Following any of these events, the 1130 host attachment returns to the basic interruptioncontrol status.Attention and power/thermal interruptions to the 1130 are also prevented by either aSystem/7 power-on reset or an 1130 Storage Access Channel reset. These interruptions arenot permitted again until a control IOCC is executed to establish a basic interruptioncontrol status.1130 Host Attachment 16-3
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GA34-0003-7File No. S7-00IBM System
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ContentsPrefaceChapter 1. Introduct
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Flagging 15-26Track Initialization
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PrefaceThis reference manual is a s
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IntroductionCHAPTER CONTENTSSystem/
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Figure 1-1. IBM 5028 Operator Stati
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• One or two analog output points
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Power Failure and Thermal WarningPo
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IBM 5010 Processor ModuleCHAPTER CO
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StorageProcessorAACycleSteal/ Featu
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The processor does not recognize in
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DATA FORMATSInput/output data can b
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The absolute form can be obtained i
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Accumulators (ACC 0 to ACC 3)Page o
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Overflow IndicatorThe overflow indi
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System/7 InterruptionsCHAPTER CONTE
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Level 1interruptionprocessing'.ros
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Interruption Mask Register and Summ
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Page of GA34-0003-6,-7As Updated Au
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The accumulator associated with the
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Page of GA34-0003-6, -7As Updated A
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The summary mask isturned on; sampl
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Processor InstructionsCHAPTER CONTE
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InstructionMnemonic'OperationcodeLo
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' rrrI !Mil,. '11111E1 luluINSTRUCT
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"" ',Pli iI 1114111111111111 111111
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Load Immediate (PLI)0 5 8 15Op code
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Store Accumulator (PST)0 5 8 15Op c
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vow wow. •1•01111111111111111
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NMI INNI 1111=111111 IM11111■1111
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11111 !III VIII I 1101 1,411111111,
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I i 1111111'1Np■I0111m PIP ,ili11
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Example:Word in accumulator 0110 11
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Exclusive ORing occurs only between
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Shift Left Circular (PSLC)0 5 8 11
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Shift Right Arithmetic (PSRA)0 5 8
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Example:PB instruction(R = 110 spec
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Branch and Link Long (PBALL)0 5 8 1
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Branch Conditional (PBC►0 5 8 9 1
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Branch and Unmask Long (BUL) (5010
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Skip Conditional (PSKC)0 5 8 9 15Op
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Example:0 5 8 15PAS instruction(loc
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Load from Register (PLR)0 5 8 15Op
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Load Processor Status (PLPS)0 5 8 1
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Write IAR Backup (WIB) (5010 Proces
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Store Indicators (STI) (5010 Proces
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Executing the OR-to-mask instructio
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the process position. If the system
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Read Protect Key (RPK)0 5 8 11 16 2
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Module address field:Module address
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11111E111111111 M11111111•11111 1
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1111111111111111111111■11•11111
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Sixteen bits of additional module i
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1 REG 1---LEVEL0 10 0 2 1 20 0 0 03
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CTL CHK (Control Check) LightThis l
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1111■111111,11,11N I IIIADDRESS L
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CHECK CONTROL SwitchThis three-posi
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START KeyPressing the start key cau
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The processor module contains two 1
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6-4 GA34-0003II I 1 1 III 111 1111
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.11.1111111.111 MP I 111.10114P III
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1111 Minn. 11111111R !VW IMF" !PFLI
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The ACCA must be selected in order
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111.1111 111111 N uData and control
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I II III• 1111111111111111 1•11
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Significant Bits Meaning7* Data set
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I■ 0=11 1111111 MEM11 1111111111
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". — •• 11•111•MI !IF lim
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V IIF 1,1 NM IICONTROL CHARACTERS A
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Character SynchronizationCharacter
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Bit 1-Reserved.Bit 2-Transmit Opera
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1,114plilloi 1110 1111 1111.11 VI P
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1 1 - 1111=111111111 111M 1111 111
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The 5028 Operator Station (Figure 9
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Thickness Paper - .004 + .0003" (0,
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Character bit position 84 Tape move
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If the operator station motor is no
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Feed Tape and Print0 5 8 11 16 20 2
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Read 1SW0 5 8 11 16 20 26 31Op code
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The 5014 Analog Input Module Model
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Convert Analog Input with External
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Read ISW0 5 8 11 16 20 26 31Op code
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10-8 GA34-0003
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11111811111111.1.1.14.111.1111I II
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" 11, 141MINMIIIIF I WPM P IP !! 11
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Read and Convert ADC0 5 8 11 16 20
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Device Status Word (DSW): The 16 bi
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1411111111,1111111111n 111The 5014
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Convert Analog Input with External
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12-6 GA34-0003
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The 5012 Multifunction Module Model
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MODULE DEVICE ADDRESSESANALOG INPUT
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The range bits (RRR) in the control
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H1111111111111 1111.111111HIVRead A
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I/0 CommandsThe prepare I/O and hal
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Data stored in the register can hav
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If a particular amplifier gain was
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' 14 111•141111111111111011114111
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Read Digital Input Reference Regist
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Digital Input Groups Without Proces
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CIA ^iN1i Ma IIl AMINNNP u 11.!..11
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Write Analog Output Holding Registe
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1111111■11111111101=11111.1111111
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=111111111111111111 1 11 1 11111111
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DataThe data byte contains either d
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Read CommandsAll read commands are
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Write Null Acknowledge: This code (
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Area Station Local I/O Guidance Cha
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2791/2793 Adapter Critical timingIn
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BeginDSC* 05Write(AS enters data mo
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oww1111111111111111111111111,1,, V
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Bit 15 in the R register can be set
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The 5013 Digital I/O Module Model A
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The prepare I/O command is used as
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Read Digital Input RegisterO 5 8 11
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Set Digital Input Interrupt Control
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DIGITAL OUTPUT CONTROLThe Digital O
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The 2792 Remote Communications Cont
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Data TransmissionInformation is tra
Page 248 and 249: The functions of the five bytes in
Page 250 and 251: Code nameHexBit patternResponse Com
Page 252 and 253: Read End Acknowledge: This code (he
Page 254 and 255: Begin Diagnostic: This code (hexade
Page 256 and 257: Page of GA34-0003-6, -7As Updated A
Page 258 and 259: Command SequencesThe 2790 Control m
Page 260 and 261: An area station requiring service l
Page 262 and 263: Set Diagnostic Mode0 5 8 11 16 20 2
Page 264 and 265: 14-32 GA34-0003
Page 266 and 267: FUNCTIONAL DESCRIPTIONThe IBM 5022
Page 268 and 269: FILE ORGANIZATIONEach surface of ea
Page 270 and 271: Sector Identifier FormatEach identi
Page 272 and 273: If fewer than 128 words are to be t
Page 274 and 275: When the IPL operation starts, the
Page 276 and 277: Recalibrate Operation: A recalibrat
Page 278 and 279: 1111 11 I 111111111111WRead Initial
Page 280 and 281: If an error is detected during a da
Page 282 and 283: None of the data read is transferre
Page 284 and 285: Error and Status ConditionsErrors d
Page 286 and 287: Significant Bits Meaning5* No recor
Page 288 and 289: Significant Bits Meaning3 Seek chec
Page 290 and 291: FLAGGINGThe condition of a track su
Page 292 and 293: Track Initialization ProceduresThe
Page 294 and 295: Bit 5—No Record FoundIt should be
Page 296 and 297: 15-32 GA34-0003
Page 300 and 301: Interruptions to System/7The progra
Page 302 and 303: Initiate Read0 16 21 24 31111111Add
Page 304 and 305: Device Status Word (DSW): The 16-bi
Page 306 and 307: 16-10 GA34-0003
Page 308 and 309: The IBM 5024 I/O Attachment Enclosu
Page 310 and 311: III 1111•1111111111•1111111 III
Page 312 and 313: 11111 1 11•1111111111111111111111
Page 314 and 315: Reset 5024The reset 5024 resets the
Page 316 and 317: 2502 Card Reader Translate TableA 2
Page 318 and 319: I/O Transfer BlockThe address of th
Page 320 and 321: Status Word 1.0 152502 status buffe
Page 322 and 323: Status Word 2.0 15Status word 1% St
Page 324 and 325: 1 1 111111111111111111111111111•1
Page 326 and 327: IMP P 1111,1111.11,11311111 I MP 11
Page 328 and 329: 11 11 1111111111 1 1111111111111111
Page 330 and 331: algaaaagIrlug",',/"'", BeltPosition
Page 332 and 333: • Disable Attention Interrupt 110
Page 334 and 335: Status Word 1.0 15aStatus word 1•
Page 336 and 337: Status Word 2.15Status word 1N+1Res
Page 338 and 339: Interrupt PresentationThe printer a
Page 340 and 341: 17-30 GA34-0003
Page 342 and 343: Add immediateMnemonicExecutiontime
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Page 346 and 347: BranchMnemonicExecutiont i me (ns)O
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Branch conditionalMnemonicExecution
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Exclusive OR registertMnemonicExecu
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Level exitMnemonicExecutiontime (ns
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Load immediateMnemonicExecutiontime
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OR registerMnemonicExecutiontime (n
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Read protect key (provided only wit
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1111■11111■111111111 1 11111111
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StopMnemonicExecutiontime Ins)Op co
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SubtractMnemonicExecutiontime (ns)O
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A-26 GA34-0003
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PIO instruction Function ModifierDe
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1111111■111111PIO instruction Fun
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Valid responses to 2790 read comman
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Interrupt status wordsDevice0 1 2 3
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Device status word (2502, 5024 with
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11.1 11111 11110•11111111111.1111
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5028ConsoleShift/ 5028BSCAACCAContr
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5028ConsoleShift/ 5028BSCAACCAContr
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triNtitTIBitRanges and bit values (
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.••■• III II III 11111.•
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E-6 GA34-0003
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Verifydata beforewrite analogoutput
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Prepare I/OSet referenceregisterYes
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F-6 GA34-0003IIII•1111■•■
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G-2 GA34-0003
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analog signal resolution (continued
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cycle steal feature data flow 2-3cy
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forced interruption control, digita
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initial program load (IPL) to Syste
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111111•1111111111■ IllO (OR) in
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ead, 5022 Disk Storage Module (cont
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11111111111111111■1 1111111 11111
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X-16 GA34-0003
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GA34-0003-7Your comments, please ..
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I 111111111111111.1 I MEM II 1 1111
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