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IBM System/7 Functional Characteristics - All about the IBM 1130 ...

IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Device Control Block (DCB)The DCB is an eight word area in storage set up by <strong>the</strong> user's program and contains <strong>the</strong>information needed to perform a read cycle steal or write cycle steal operation. The formatof <strong>the</strong> DCB is as follows:0 15Word 0 ID AWord 1. Reserved A + 1Word 2 Reserved A + 2Word 3 Reserved A + 3Word 4 Reserved A + 4Word 5 XI Priority option (bit 0) A +tWord 6 Word count A + 6Word 7 Starting data address A + 7A—<strong>the</strong> starting address in storage of <strong>the</strong> DCB. This address is <strong>the</strong> contents of <strong>the</strong> index register (R), or<strong>the</strong> accumulator if R=000, specified in <strong>the</strong> read cycle steal or write cycle steal command.IDThe ID word has <strong>the</strong> following format:0 2 9 11 15F C T S1 1 1 1 1 1 1<strong>All</strong> fields are <strong>the</strong> same as for write initialize or read initialize.Priority OptionIf word 5 bit 0 is on at DCB fetch time, a higher priority will be assigned to <strong>the</strong> device at<strong>the</strong> interface multiplexer.Word CountThe word count is <strong>the</strong> number of words to be transferred during <strong>the</strong> operation. If <strong>the</strong>word count is 0 when <strong>the</strong> DCB is fetched, a normal end interruption occurs immediatelyand <strong>the</strong> operation is suppressed. The word count is fetched by <strong>the</strong> subchannel in<strong>the</strong> 5022 attachment and is decremented by 1 for each word transferred until aninterruption condition is met. If <strong>the</strong> data transfer continues successfully until <strong>the</strong> countequals 0, an interruption occurs indicating <strong>the</strong> successful end of <strong>the</strong> operation. If <strong>the</strong>word count goes to 0 before <strong>the</strong> end of a sector:Read cycle steal—The remainder of <strong>the</strong> sector is read (but no data is transferred) and <strong>the</strong>check character is verified prior to <strong>the</strong> end interruption.Write cycle steal—The remainder of <strong>the</strong> sector is set to all O's and <strong>the</strong> appropriate checkcharacter is accumulated and written at <strong>the</strong> end of <strong>the</strong> sector prior to <strong>the</strong> end interruption.Data AddressThe data address is <strong>the</strong> address of <strong>the</strong> first word of data to be transferred. This parameteris fetched by <strong>the</strong> 5022 subchannel which holds it in a register, updates it, and presentsit to <strong>the</strong> channel during data transfer. On a read operation, <strong>the</strong> first word from <strong>the</strong>sector specified in <strong>the</strong> DCB is stored at this address, <strong>the</strong> next word from that sector isstored at <strong>the</strong> next sequential address and so on until <strong>the</strong> read operation ends. On a writeoperation, <strong>the</strong> first word in <strong>the</strong> data table (pointed to by <strong>the</strong> data address field) is <strong>the</strong>first word written onto <strong>the</strong> sector specified in <strong>the</strong> DCB until <strong>the</strong> operation ends.The read or write operation continues, crossing over sector boundaries, until a terminationcondition is met. As each new sector is detected during <strong>the</strong> operation, its ID ischecked to ensure that it is, indeed, <strong>the</strong> next sequential sector.<strong>IBM</strong> 5022 Disk Storage Module 15-19

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