IBM System/7 Functional Characteristics - All about the IBM 1130 ...

Instruction Address Register (IAR)The instruction address register (IAR) holds the address of the next instruction to beexecuted (see Figure 2-2). During program execution the contents of the IAR are placed inthe storage address register for fetching the contents of the next location in storage.The IAR is incremented immediately after its contents have been placed in the storageaddress register. Consequently, the IAR contains the address of the next location instorage at the time the current instruction is executed.For example, assume that the following instruction is being executed:Storage Storage contents Instruction address registerAddress 0 15 0 150500 Instruction0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1I I I I I I I I I I I I I I I I I I I I I I I I I i I I I0 5 0 1Points to0501 Instruction or dataI I I II I I I I I I I I I IThe 16-bit IAR contains the address of the storage word immediately following theinstruction being executed. In most cases, this next word is the next instruction to beexecuted. Sometimes, however, the contents of the IAR are changed as a result of theinstruction being executed. Execution of a branch instruction, for example, can causeaccessing of the next instruction from a storage location other than the locationimmediately following the current instruction.The System/7 processor also has three backup instruction address registers (IARB 1,IARB 2, and IARB 3) for priority interruption levels 1, 2, and 3, respectively. When achange of interruption level occurs on level 1, 2, or 3, the IAR is automatically savedin the IARB for the level that is interrupted. (There is no need for an IARB for level 0because level 0 is the highest priority level and cannot be interrupted. Therefore, IARB 0is used for the old IAR and will point to the address of the last instruction executed.)When a return is made to the interrupted level, processing will resume at the locationspecified by the saved address.The contents of the IAR or any IARB can be displayed on the operator console. Thecontents of the IAR can also be modified via the console switches.Index Registers (XR1 to XR7)The System/7 processor has seven index registers for each of the four priority interruptionlevels (see Figure 2-2). Each index register has 16 data bits plus 2 parity bits. The contentsof index registers can be used in generating effective addresses as described in Chapter 4under "Effective Address Generation." The contents of index registers can also be manipulatedin arithmetic and logical operations. These manipulations are explained in thedetailed instruction descriptions in Chapter 4 "Processor Instructions."The contents of any selected index register can be displayed on the operator console ormodified via the console switches.2-10 GA34-0003