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IBM System/7 Functional Characteristics - All about the IBM 1130 ...

IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Programming Note: The terminate command, instead of <strong>the</strong> four read data or write datacommands, must be issued following a data-service interruption request.Condition code errors to read or write operations can be interrogated to determine ifan overrun interrupt is pending or if no interrupt should be expected. If condition code1 is received, <strong>the</strong> DSW can be read to determine if <strong>the</strong> error was command reject or datacheck. If command reject, no o<strong>the</strong>r interruption will be presented. If data check, <strong>the</strong> programwill receive an overrun interrupt. If condition code 2 is received, it indicates that<strong>the</strong>re is ano<strong>the</strong>r interruption pending. This interruption may indicate overrun or anyo<strong>the</strong>r error condition, such as, drive became not ready or equipment check.Looping on a halt I/O command before <strong>the</strong> file becomes ready will keep <strong>the</strong> file frombecoming ready. If a halt I/O or system reset occurs, a load next sector ID or seek operationmust be performed to select a head before doing a read, write, read verify or formattrack operation. If a halt I/O is performed when <strong>the</strong> file is not ready due to an unsafecondition, <strong>the</strong> file will become ready. If <strong>the</strong> file is prepared to interrupt, it will present aninterrupt with <strong>the</strong> attention bit (0) on.Read Cycle Steal (Cycle Steal Feature)0 5 8 11 16 20 26 31Op code R Fun Zeros Mod DA MA0 0 0 0 1 XX I 1 0 0 0 0 0 0 0 0 0 1 ******XXXXXXI I I I 1 I 1 1 1 1 1 1 1 1 1 1 I 1 1 1 I 1 1 1 1.."..."'"\e""•••••"0 8-F C 0 1 0 0-3 XThis command causes <strong>the</strong> device to cycle steal data from <strong>the</strong> disk into main storage.The index register (R), or <strong>the</strong> accumulator if R =000, contains <strong>the</strong> starting address of<strong>the</strong> DCB. The DCB contains <strong>the</strong> information needed to perform <strong>the</strong> operation. Thedisk module is busy to all commands, except status reads, from <strong>the</strong> time this commandis issued until <strong>the</strong> channel end interruption.Read Residual Address (Cycle Steal Feature)0 5 8 11 16 20 26 31Op code R Fun Zeros Mod DA MA0 0 0 0 1 XXX 0 1 0 0 0 0 0 0 1 1 1 1 *** ***XXXXXXI I I I II II I I I I III I 1 1 1 1 I 1 1 1 10 8-F 4 0 F 0 0-3 XThis command reads <strong>the</strong> contents of <strong>the</strong> data address register which is updated by <strong>the</strong>5022 attachment sub channel. The purpose of this command is to indicate to <strong>the</strong>program, for recovery purposes, <strong>the</strong> exact point during data transfer at which a subchannelerror or exception condition occurred. The data address register in <strong>the</strong> subchannel is notreset by this command or by a halt I/O command. It is reset by a system reset. Theread residual address command does not cause an interruption.If a check character error for <strong>the</strong> sector ID is detected, <strong>the</strong> data address register contains<strong>the</strong> address associated with <strong>the</strong> first word of that sector. The any-error bit (bit 3), norecord-foundbit (bit 5), channel-end bit (bit 11), device-end bit (bit 13), and <strong>the</strong> readISWEX bit (bit 15) are set in <strong>the</strong> ISW. The file-data-check bit (bit 4) is set in <strong>the</strong> ISWEX.During a multisector operation, if <strong>the</strong> ID word is not <strong>the</strong> next sequential ID, <strong>the</strong> dataaddress register contains <strong>the</strong> address associated with <strong>the</strong> first word of <strong>the</strong> new sector.The any-error bit (bit 3), channel-end bit (bit 11), device-end bit (bit 13), and <strong>the</strong>read-ISWEX bit (bit 15) are set in <strong>the</strong> ISW. The missing-address-mark bit (bit 1) is set in<strong>the</strong> ISWEX.<strong>IBM</strong> 5022 Disk Storage Module 15-15

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