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IBM System/7 Functional Characteristics - All about the IBM 1130 ...

IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Page of GA34-0003-6, -7As Updated August 20, 1976By TNL GN34-0340DCB Word 6 (Word count)This word contains a count of <strong>the</strong> number of words to be transmitted or received.DCB Word 7 (Starting data address)This word contains <strong>the</strong> starting address in <strong>System</strong>/7 storage to be used in fetching or storingdata for a transmit or receive operation. After <strong>the</strong> DCB has been placed in <strong>the</strong> variousBSCA registers, this address is placed in <strong>the</strong> BSCA SAR which determines <strong>the</strong> storageaddress of <strong>the</strong> data being handled by <strong>the</strong> BSCA. On transmit operations, one word is takenfrom storage by a cycle steal operation and is transmitted as two consecutive characters. Onreceive operations, two characters are received and stored in a buffer. Then a cycle stealoperation is initiated to transfer <strong>the</strong>m to storage as one word. If an odd number of charactersis received, zeros are loaded into <strong>the</strong> low order byte.Write Address0 5 8 11 16 20 26 31Op code R Fun Zeros Mod DA MA0 0 0 0 1 XXX 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 01 I I I II II I I I I III 1 1 1 111110 8-F 2 0 3 3 0 0This command stores <strong>the</strong> contents of bits 8-15 from <strong>the</strong> register specified by <strong>the</strong> Rfield, or <strong>the</strong> accumulator if R=000, into <strong>the</strong> BSCA storage address register (SAR) bits8-15, to form a partial DCB address. Condition code 2 is set if <strong>the</strong> BSCA is busy oran interruption is pending. This command does not cause an interruption.Initiate I/O0 5 8 11 16 20 26 31Op code R Fun Zeros Mod DA MA0 0 0 0 1 X X X 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0I I I I 1 1 1 1 I I I I 1 1 1 1 1 1 1 1 1 1 1 1 10 8-F 2 0 7 3 0 0This command stores <strong>the</strong> contents of bits 8 to 15 from <strong>the</strong> register specified by <strong>the</strong> Rfield, or <strong>the</strong> accumulator if R= 000, into <strong>the</strong> <strong>the</strong> BSCA storage address register (SAR),bits 0 to 7, to complete <strong>the</strong> DCB address. Condition code 2 is set if <strong>the</strong> BSCA is busy oran interruption is pending. If <strong>the</strong> BSCA has not been prepared, condition code 1 is returnedand command reject (bit 1) is set in <strong>the</strong> direct control channel status word. If <strong>the</strong>BSCA has been prepared, <strong>the</strong> DCB is fetched from storage by <strong>the</strong> adapter. Subsequentaction depends on <strong>the</strong> control bit(s) in word 3 of <strong>the</strong> DCB as described earlier in thischapter.8-8 GA34-0003

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