IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Bit 1-Reserved.Bit 2-Transmit Operation. A 3-second timeout starts, and request to send to the modemis turned on. When clear to send from the modem comes on, the timeout is turned offand the BSCA begins transferring data from System/7 storage. A normal channel-end/device-end interruption request to the System/7 processor is generated when:• A COD character is transmitted and the chaining flag (described later in this section)is off.• When the word count becomes 0 and the chaining flag is off.If the data set ready line from the modem is off, or if receive mode is on while attemptingto transmit, an error interruption occurs immediately, setting on bit 1 (commandreject) in the ISW. Receive mode will be on if the previous operation was a receive operationand a COD character was not received.Failure to receive clear to send from the modem within the 3-second timeout periodcauses an interruption, setting on bit 3 (timeout) in the ISW. Transmit mode is turned offand request to send to the modem is discontinued after the PAD character (eight 1-bits) issent following a COD character or block check character (BCC) if required.Bit 3-Allow Transparent Control. The ability to transmit control sequences while in transparenttext mode is provided by setting on this bit. It should be set on in the final DCBused for a transparent text operation. It can be used only in a DCB following a block oftransparent text.If the BSCA is not in transparent text mode when this bit is presented, an error interruptionoccurs setting on bit 1 (command reject) in the ISW.Programming note. It is suggested that bit 3 be used only with a word count of 1 (transparentend of text-DLE ETX; transparent end of transmission block-DLE ETB, etc.) toavoid unpredictable results should a data character and a DLE character have the samebit configuration.Bit 4-Enable Terminal. If the host attach switch on the System/7 console is in the enableposition, setting on this bit sets the data terminal ready and enables detection of dataset ready. In a switched network, if the host attach switch is in the enable and IPLposition, a. ring indication also sets the data terminal ready. In a non-switched network, thedata terminal is ready at all times.Bit 11 (start 3-second timer) may be used with bit 4 to limit the time allowed by theBSCA for the data set to get ready. If the data set is not ready within this time, an interruptionoccurs, setting on bit 3 (timeout) in the ISW.Bit 5-Disable Terminal. Setting on this bit discontinues the data terminal ready line to thedata set, to allow disconnecting from a switched network. During this period (3 seconds)the BSCA is busy. At the completion of the disconnect, the BSCA causes an interruption ifthe chaining flag in word 5 of the DCB is off. Data terminal ready cannot be discontinuedon a leased line.Note: If the System/7 is dialed up erroneously, or if a switched line connection is interruptedduring BSCA communications, then the data terminal ready line to the data setmust be discontinued before line connection can be re-established. There are 3 ways ofdoing this:1. Set on bit 5 to disable the terminal.2. Put the host attach switch on the operator console in the disable positionmomentarily.3. An automatic internal timer disables the terminal after 2.5 minutes.8-6 GA34-0003
Bit 6-Reserved.Bit 7-Parity 1. This bit is used to maintain even parity in the high order byte of this controlword.Bit 8-Set ASCII Mode. Setting this bit on allows communication using ASCII code. Whenoff, the BSCA recognizes EBCDIC code.Bit 9-Reserved.Bit 10-Start 2-second Timer. This bit is used to start a 2-second interval after which theBSCA interrupts. Timeout (bit 3) in the ISW is not set on.Bit 11-Start 3-second Timer. This bit is used to start a 3-second interval after which theBSCA interrupts. Timeout (bit 3) in the ISW is not set on. This bit may also be usedwith bit 0 and/or with bit 4 to limit time.Bits 12, 13, and 14 Reserved.Bit 15-Parity 2. This bit is used to maintain even parity in the low order byte of thiscontrol word.Following are the valid bit combinations for use in word 3. A parity error detected inword 3 causes an interruption, setting on bit 1 (command reject) in the ISW. Correct(even) parity in word 3 with an invalid bit combination causes unpredictable results.General Control FunctionsHex Function0900 Enable0911 Enable with 3-second timeout0500 Disable0021 2-second timeout0011 3-second timeoutEBCDIC Control FunctionsHex Function8100 Receive8111 Receive with 3-second timeout2100 Transmit1100 Transmit in transparent text modeASCII Control FunctionsHex Function8181 Receive8190 Receive with 3-second timeout2181 TransmitDCB Word 4 (Chain address)This word contains the address of the DCB to be used (chained to) when the current bytecount is decremented to 0 or a COD character is recognized, and the chaining flag(bit 1) is on in word 5.DCB Word 5 (Chaining flag)Bit 0-Reserved. This bit is not used by the BSCA but must be set to 0.Bit 1-Chaining Flag. When on, this bit indicates that word 4 contains the address of thechained-to DCB.Bits 2-15. Not used by the BSCA but must be 0.Binary Synchronous Communications Adapter 8-7
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GA34-0003-7File No. S7-00IBM System
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ContentsPrefaceChapter 1. Introduct
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Flagging 15-26Track Initialization
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PrefaceThis reference manual is a s
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IntroductionCHAPTER CONTENTSSystem/
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Figure 1-1. IBM 5028 Operator Stati
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• One or two analog output points
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Power Failure and Thermal WarningPo
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IBM 5010 Processor ModuleCHAPTER CO
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StorageProcessorAACycleSteal/ Featu
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The processor does not recognize in
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DATA FORMATSInput/output data can b
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The absolute form can be obtained i
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Accumulators (ACC 0 to ACC 3)Page o
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Overflow IndicatorThe overflow indi
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System/7 InterruptionsCHAPTER CONTE
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Level 1interruptionprocessing'.ros
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Interruption Mask Register and Summ
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Page of GA34-0003-6,-7As Updated Au
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The accumulator associated with the
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Page of GA34-0003-6, -7As Updated A
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The summary mask isturned on; sampl
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Processor InstructionsCHAPTER CONTE
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InstructionMnemonic'OperationcodeLo
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' rrrI !Mil,. '11111E1 luluINSTRUCT
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"" ',Pli iI 1114111111111111 111111
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Load Immediate (PLI)0 5 8 15Op code
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Store Accumulator (PST)0 5 8 15Op c
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vow wow. •1•01111111111111111
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NMI INNI 1111=111111 IM11111■1111
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11111 !III VIII I 1101 1,411111111,
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I i 1111111'1Np■I0111m PIP ,ili11
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Example:Word in accumulator 0110 11
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Exclusive ORing occurs only between
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Shift Left Circular (PSLC)0 5 8 11
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Shift Right Arithmetic (PSRA)0 5 8
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Example:PB instruction(R = 110 spec
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Branch and Link Long (PBALL)0 5 8 1
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Branch Conditional (PBC►0 5 8 9 1
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Branch and Unmask Long (BUL) (5010
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Skip Conditional (PSKC)0 5 8 9 15Op
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Example:0 5 8 15PAS instruction(loc
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Load from Register (PLR)0 5 8 15Op
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Load Processor Status (PLPS)0 5 8 1
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Write IAR Backup (WIB) (5010 Proces
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Store Indicators (STI) (5010 Proces
Page 96 and 97: Executing the OR-to-mask instructio
Page 98 and 99: the process position. If the system
Page 100 and 101: Read Protect Key (RPK)0 5 8 11 16 2
Page 102 and 103: Module address field:Module address
Page 104 and 105: 11111E111111111 M11111111•11111 1
Page 106 and 107: 1111111111111111111111■11•11111
Page 108 and 109: Page of GA34-0003-6, -7As Updated A
Page 110 and 111: Sixteen bits of additional module i
Page 112 and 113: 1 REG 1---LEVEL0 10 0 2 1 20 0 0 03
Page 114 and 115: CTL CHK (Control Check) LightThis l
Page 116 and 117: 1111■111111,11,11N I IIIADDRESS L
Page 118 and 119: CHECK CONTROL SwitchThis three-posi
Page 120 and 121: START KeyPressing the start key cau
Page 122 and 123: The processor module contains two 1
Page 124 and 125: 6-4 GA34-0003II I 1 1 III 111 1111
Page 126 and 127: .11.1111111.111 MP I 111.10114P III
Page 128 and 129: 1111 Minn. 11111111R !VW IMF" !PFLI
Page 130 and 131: The ACCA must be selected in order
Page 132 and 133: 111.1111 111111 N uData and control
Page 134 and 135: I II III• 1111111111111111 1•11
Page 136 and 137: Significant Bits Meaning7* Data set
Page 138 and 139: I■ 0=11 1111111 MEM11 1111111111
Page 140 and 141: ". — •• 11•111•MI !IF lim
Page 142 and 143: V IIF 1,1 NM IICONTROL CHARACTERS A
Page 144 and 145: Character SynchronizationCharacter
Page 150 and 151: 1,114plilloi 1110 1111 1111.11 VI P
Page 154 and 155: 1 1 - 1111=111111111 111M 1111 111
Page 156 and 157: The 5028 Operator Station (Figure 9
Page 158 and 159: Thickness Paper - .004 + .0003" (0,
Page 160 and 161: Character bit position 84 Tape move
Page 162 and 163: If the operator station motor is no
Page 164 and 165: Feed Tape and Print0 5 8 11 16 20 2
Page 166 and 167: Read 1SW0 5 8 11 16 20 26 31Op code
Page 168 and 169: The 5014 Analog Input Module Model
Page 170 and 171: Convert Analog Input with External
Page 172 and 173: Read ISW0 5 8 11 16 20 26 31Op code
Page 174 and 175: 10-8 GA34-0003
Page 176 and 177: 11111811111111.1.1.14.111.1111I II
Page 178 and 179: " 11, 141MINMIIIIF I WPM P IP !! 11
Page 180 and 181: Read and Convert ADC0 5 8 11 16 20
Page 182 and 183: Device Status Word (DSW): The 16 bi
Page 184 and 185: 1411111111,1111111111n 111The 5014
Page 186 and 187: Convert Analog Input with External
Page 188 and 189: 12-6 GA34-0003
Page 190 and 191: The 5012 Multifunction Module Model
Page 192 and 193: MODULE DEVICE ADDRESSESANALOG INPUT
Page 194 and 195: The range bits (RRR) in the control
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H1111111111111 1111.111111HIVRead A
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I/0 CommandsThe prepare I/O and hal
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Data stored in the register can hav
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If a particular amplifier gain was
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' 14 111•141111111111111011114111
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Read Digital Input Reference Regist
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Digital Input Groups Without Proces
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CIA ^iN1i Ma IIl AMINNNP u 11.!..11
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Write Analog Output Holding Registe
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1111111■11111111101=11111.1111111
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=111111111111111111 1 11 1 11111111
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DataThe data byte contains either d
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Read CommandsAll read commands are
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Write Null Acknowledge: This code (
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Area Station Local I/O Guidance Cha
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2791/2793 Adapter Critical timingIn
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BeginDSC* 05Write(AS enters data mo
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oww1111111111111111111111111,1,, V
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Bit 15 in the R register can be set
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The 5013 Digital I/O Module Model A
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The prepare I/O command is used as
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Read Digital Input RegisterO 5 8 11
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Set Digital Input Interrupt Control
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DIGITAL OUTPUT CONTROLThe Digital O
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The 2792 Remote Communications Cont
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Data TransmissionInformation is tra
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The functions of the five bytes in
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Code nameHexBit patternResponse Com
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Read End Acknowledge: This code (he
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Begin Diagnostic: This code (hexade
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Page of GA34-0003-6, -7As Updated A
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Command SequencesThe 2790 Control m
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An area station requiring service l
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Set Diagnostic Mode0 5 8 11 16 20 2
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14-32 GA34-0003
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FUNCTIONAL DESCRIPTIONThe IBM 5022
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FILE ORGANIZATIONEach surface of ea
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Sector Identifier FormatEach identi
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If fewer than 128 words are to be t
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When the IPL operation starts, the
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Recalibrate Operation: A recalibrat
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1111 11 I 111111111111WRead Initial
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If an error is detected during a da
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None of the data read is transferre
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Error and Status ConditionsErrors d
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Significant Bits Meaning5* No recor
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Significant Bits Meaning3 Seek chec
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FLAGGINGThe condition of a track su
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Track Initialization ProceduresThe
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Bit 5—No Record FoundIt should be
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15-32 GA34-0003
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I III 1111111111111111111111111111
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Interruptions to System/7The progra
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Initiate Read0 16 21 24 31111111Add
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Device Status Word (DSW): The 16-bi
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16-10 GA34-0003
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The IBM 5024 I/O Attachment Enclosu
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III 1111•1111111111•1111111 III
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11111 1 11•1111111111111111111111
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Reset 5024The reset 5024 resets the
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2502 Card Reader Translate TableA 2
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I/O Transfer BlockThe address of th
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Status Word 1.0 152502 status buffe
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Status Word 2.0 15Status word 1% St
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1 1 111111111111111111111111111•1
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IMP P 1111,1111.11,11311111 I MP 11
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11 11 1111111111 1 1111111111111111
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algaaaagIrlug",',/"'", BeltPosition
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• Disable Attention Interrupt 110
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Status Word 1.0 15aStatus word 1•
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Status Word 2.15Status word 1N+1Res
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Interrupt PresentationThe printer a
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17-30 GA34-0003
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Add immediateMnemonicExecutiontime
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Alter storage key (provided only wi
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BranchMnemonicExecutiont i me (ns)O
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Branch conditionalMnemonicExecution
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Exclusive OR registertMnemonicExecu
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Level exitMnemonicExecutiontime (ns
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Load immediateMnemonicExecutiontime
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OR registerMnemonicExecutiontime (n
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Read protect key (provided only wit
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1111■11111■111111111 1 11111111
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StopMnemonicExecutiontime Ins)Op co
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SubtractMnemonicExecutiontime (ns)O
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A-26 GA34-0003
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PIO instruction Function ModifierDe
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1111111■111111PIO instruction Fun
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Valid responses to 2790 read comman
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Interrupt status wordsDevice0 1 2 3
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Device status word (2502, 5024 with
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11.1 11111 11110•11111111111.1111
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5028ConsoleShift/ 5028BSCAACCAContr
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5028ConsoleShift/ 5028BSCAACCAContr
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triNtitTIBitRanges and bit values (
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.••■• III II III 11111.•
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E-6 GA34-0003
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Verifydata beforewrite analogoutput
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Prepare I/OSet referenceregisterYes
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F-6 GA34-0003IIII•1111■•■
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G-2 GA34-0003
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analog signal resolution (continued
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cycle steal feature data flow 2-3cy
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forced interruption control, digita
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initial program load (IPL) to Syste
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111111•1111111111■ IllO (OR) in
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ead, 5022 Disk Storage Module (cont
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11111111111111111■1 1111111 11111
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X-16 GA34-0003
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GA34-0003-7Your comments, please ..
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I 111111111111111.1 I MEM II 1 1111
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