IBM System/7 Functional Characteristics - All about the IBM 1130 ...

Page of GA34-0003-6, -7As Updated August 20, 1976By TNL GN34-0340I/0 COMMANDSThe BSCA is programmed using the prepare I/O command (as described in Chapter 4under "Input/Output Instruction") and various immediate read and immediate writecommands. The setting of the modifier field bits in the immediate commands furtherdefine the operations to be performed.All I/O commands to the BSCA must have a device address of 001100 and a moduleaddress of 000000.BSCA has its' own cycle steal function which operates independently of the optionalcycle steal feature. Messages are transferred to and from BSCA by cycle steal cycles usingparameters established by the BSCA device control block.Device Control BlockThe device control block (DCB) is an eight word area in storage set up by the user's programand contains the information needed to perform a BSCA cycle steal operation.Each receive or transmit operation starts with the cycle steal fetch of the DCB. Theaddress of the DCB is placed in the BSCA SAR by two PIO immediate write commands.The first command, write address, places the low order byte of the DCB address inpositions 8 through 15 of the BSCA SAR. An initiate I/O command then places the highorder byte of the address into the BSCA SAR to complete the address. At the completionof the initiate I/O command, the BSCA becomes busy and begins to cycle steal the DCBfrom main storage into various BSCA registers. Following the last DCB cycle, cycle stealoperations continue depending on the active control word bits.Word 0Word 1Word 2Word 3Word 4Word 5Word 6Word 70 15ReservedReservedReservedControl wordDCB chain addressIX! DCB chaining flag (bit 1)Word countStarting data addressAA + 1A + 2A + 3A + 4A + 5A + 6A + 7A—the starting address in storage of the DCB. This address is established through the execution of thewrite address and the initiate I/O commands.Word count and starting data address are not changed by the input/output operation.DCB Word 3 (Control Word)Bit 0-Receive Operation. When byte synchronization is established the BSCA beginstransferring data into System/7 storage. A normal end interruption request to theSystem/7 processor is generated:• When change of direction (COD) character is received and the chaining flag (describedlater in this section) is off.• When the word count becomes 0 and the chaining flag is off.If the data set ready line from the modem is off, or if transmit mode is on when thisoperation begins, an error interruption occurs immediately, setting on bit 1 (commandreject) in the interrupt status word (ISW). Transmit mode will be on if the previousoperation was a transmit operation and a COD character was not sent.Bit 11 (start 3-second timer) may be used with this bit to limit the time allowed by theBSCA to establish character synchronization. Failure to establish synchronization withinthis time causes an interruption, setting on bit 3 (timeout) in the ISW.Binary Synchronous Communications Adapter 8-5