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IBM System/7 Functional Characteristics - All about the IBM 1130 ...

IBM System/7 Functional Characteristics - All about the IBM 1130 ...

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Significant Bits Meaning0* Attention. The ACCA has recognized a poll from <strong>the</strong> host processor.This bit can be active only when <strong>the</strong> station control option is installedand <strong>the</strong> ACCA recognizes its own address. ISW bit 13 is also setalong with this status bit.1 Serial transmit data. This bit reflects <strong>the</strong> condition of <strong>the</strong> serial transmitline at all times. Bit 1 is used as a diagnostic aid for <strong>the</strong> transmitcircuits of <strong>the</strong> ACCA and, consequently, has meaning only to a diagnosticprogram. This bit may or may not be set when <strong>the</strong> ISW for <strong>the</strong>ACCA is read. No interruption requests are presented when this bitis set.2* Overrun. A character was received before <strong>the</strong> previous character wasstored by <strong>the</strong> <strong>System</strong>/7. ISW bit 13 is also set if <strong>the</strong> interruption requestfrom <strong>the</strong> previous character is still pending.3* End of block. When in receive mode, <strong>the</strong> ACCA has recognized anend-of-block (EOB) control character followed by a longitudinal redundancycheck (LRC) character. If <strong>the</strong> received LRC character doesnot compare with <strong>the</strong> LRC character generated by <strong>the</strong> ACCA, ISWbit 14 (data check) is also set.4 (*) Character received. One of <strong>the</strong> following conditions occurred:1. If <strong>the</strong> ACCA is in receive mode, a character o<strong>the</strong>r than end ofblock (EOB), end of transmission (EOT), longitudinal redundancycheck (LRC), upshift (US), or downshift (DS) was received.ISW bit 10 (receive mode) is also set when <strong>the</strong> resultinginterruption request is presented to <strong>the</strong> processor.2. If <strong>the</strong> ACCA is in receive status, a character o<strong>the</strong>r than US orDS was received. The summary status indicator and ISW bit 13are also set when <strong>the</strong> resulting interruption request is presentedto <strong>the</strong> processor.3. If <strong>the</strong> ACCA is operating in binary data mode, a 16-bit binaryword has been assembled by <strong>the</strong> ACCA. The summary statusindicator and ISW bits 8, 10, and 13 are also set when <strong>the</strong> resultinginterruption request is presented to <strong>the</strong> processor.Note: ISW bit 4 can be set when <strong>the</strong> ACCA has received line noiseas data.5* Time out. One of <strong>the</strong> following does not occur within a 16.5-secondtime limit:1. The ACCA responds to a transmit control command.2. The <strong>System</strong>/7 issues a transmit character command when <strong>the</strong>ACCA is in transmit status or mode.3. The ACCA receives a character when in receive mode.4. The ACCA receives a response to <strong>the</strong> transmission of an EOBcharacter.6 (*) Ready to transmit. Ei<strong>the</strong>r of <strong>the</strong> following occurs:1. The ACCA is ready to accept a new character for transmission.If <strong>the</strong> ACCA is not in transmit mode at this time, <strong>the</strong> summarystatus indicator is also set.2. A transmit control command is issued and <strong>the</strong> ACCA sensesthat <strong>the</strong> data set is ready to send.Asynchronous Communications Control Attachment 7-11

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