predicting physical design results using advanced synthesis features

PREDICTING PHYSICAL DESIGN RESULTS USINGADVANCED SYNTHESIS FEATURESShahzad Chowdry, Member Technical StaffSymmid Semiconductor Technologywww.symmidsemi.com

Objective• To explain the operation a new synthesismethodology: RC-Physical• To present the results of benchmark testscomparing RC-Physical to Wire Load Model(WLM) synthesis and Zero Wire Load Model(ZWLM) synthesisCDNLive 2007 Silicon Valley

About Symmid Semiconductor Tech• ASIC Design Services & IP firm• Headquartered in Silicon Valley• Founders are from EDA & Semiconductor industries• RTL, DFT, synthesis, physical design, low powerexperts• www.symmidsemi.comCDNLive 2007 Silicon Valley

Terms Used In This Presentation

Library Exchange Format (LEF)• Defines physical parameters for a specific technologyprocess:– physical dimensions & orientation of library cells, macros– Number of layers, layer-specific design rules, via definitions– Layer specific information: width, spacing, routing direction,resistance/um2, cap/um2• Required by physical design tools such as SOC Encounter• Not used by ‘traditional’ synthesis tools• RTL Compiler(RC) reads this lib as part of RC-PhysicalmethodologyCDNLive 2007 Silicon Valley

Capacitance Table (capTable)• Defines process-specific physical parameters also defined inLEF library, including:• number of layers & physical dimensions• via definitions• Resistance/um2 & capacitance/um2 per layer• capTable data is more detailed and tends to be more accuratethan LEF library data, as it is based on detailed parasiticextraction• Used by physical design tools and RC (RC-Physical mode)• Ignored by traditional synthesis toolsCDNLive 2007 Silicon Valley

Design Exchange Format (DEF)• DEF files are used by place and route tools to store logicaland physical information about a design• Logical Information: netlist connectivity• Physical Information: floorplan specs, physical location ofevery design instance, routing geometry data• Floorplans are stored as DEF files. As the design is placedand routed, additional information is added to the DEF file.• Used by physical design tools and RC (RC-Physical mode)• Ignored by traditional synthesis toolsCDNLive 2007 Silicon Valley

Wire Load Model (WLM)• Estimates interconnect(wire) delay• Lookup table that returns net resistance or capacitance basedon net fanout and the size of the block encapsulating the net.• The most accurate way of calculating wire delay is based onactual physical length of the wire. WLMs are a pooralternative method used by synthesis tools that traditionallycan’t generate or can’t access physical wire informationCDNLive 2007 Silicon Valley

set_load File• A file containing the name and corresponding capacitive loadvalue for every net in a design.• The file uses the SDC command “set_load” to specify the netname and load• Capacitive load value applied to net is the sum of all port, pinand net capacitancesCDNLive 2007 Silicon Valley

Quality of Results (QoR)• A set of synthesis metrics commonly used to measure to howeffective a synthesis run was at optimizing a design.• QoR Metrics:– Worst Negative Slack (WNS)– Total Negative Slack (TNS)– Area– Instance Count– Dynamic Power– Leakage Power• QoR numbers from WLM synthesis, ZWLM synthesis and RC-Physical will be compared later in this presentation to helpdetermine which methodology produced the best results.CDNLive 2007 Silicon Valley

Predictability• A measure of how accurately synthesis QoR and set_loadnumbers match the physical design results. Also known as‘correlation’• Good predictability means logic designers can trust that thesynthesis QoR numbers are valid indicators of final QoRnumbers measured after physical implementation.• Bad predictability means the synthesis tool has difficultydifferentiating paths that violate timing from those that don’t.Poorly predictive synthesis tools will likely try to improve thetiming of paths that aren’t violators and/or never optimizepaths that truly do violate timing.CDNLive 2007 Silicon Valley

Synthesis Methodologies

WLM & ZWLM Methodologies.libRTL.sdcRTL CompilerRead library dataRead HDLElaborateApply ConstraintsDefine DFT Controls & DRCMapIncremental OptimizationGenerate ReportsWrite Output Files• A traditional synthesis flow.No physical information isconsidered.• Synthesis flow used by SSTwhen WLMs or ZWLMswere used.• Difference between WLMand ZWLM synthesis– WLM: 10% clock uncert + netdelay estimated by foundryWLM– ZWLM: 30% clock uncert only.Wire delay is zero.set_load.sdc.libRPTsCDNLive 2007 Silicon Valley

RC-Physical Methodology• Introduced by Cadence in RTL Compiler 7.1• Incorporates physical/process data intointerconnect delay calculations• Consists of two RTL Compiler features:– Physical Layout Estimation (PLE)– QoS PredictionCDNLive 2007 Silicon Valley

Physical Layout Estimation (PLE)• Method/model to calculate interconnect delay.• An alternative to WLM.• Uses a proprietary algorithm that takes design & vendorprocess data into account.• Other significant differences between WLMs and PLE aresummarized below:*Data from Cadence based on 100 tapeouts using PLECDNLive 2007 Silicon Valley

RC Synthesis Flow With PLE EnabledCommands required to enable PLE are shown in orange.lib.LEFcapTableRTL CompilerRead tech libRead physical lib infoset_attr libraryset_attr lef_libraryset attr cap_table_fileRTL.sdc.DEFRead Verilog Source FilesElaborate DesignApply ConstraintsDefine DFT Controls & DRCread_hdlelaborateread_sdcset_attr def_fileMap (PLE Driven)CDNLive 2007 Silicon Valley

Nets PLE Can’t Estimate• PLE can accurately calculate delay “short nets” whichcomprise 80% – 90% of the total nets in a design.• Remaining 10%-20% cannot be estimated by any pre-layoutalgorithm. Nets that fall into this category include:– Nets connecting to macros– Nets that route around obstacles– Long nets that span the die to interconnect clusters of logic– Long nets that connect to block level pins that are far removedfrom each other physically• RC-Physical uses the QoS Prediction feature to calculate netloads for this class of netCDNLive 2007 Silicon Valley

QoS Prediction• Second feature that RC-Physical is comprised of• Targets the long nets PLE can’t estimate.• Invokes SOC Encounter’s Silicon Virtual Prototyping (SVP)feature from within the RC session• Uses SVP to perform trial place and route so loading on longnets can be estimated properly.• New RC command: predict_qos calls this feature• Works in concert with PLE.• PLE handles delay calculation during structuring phase ofsynthesis. predict_qos is enabled AFTER mapping iscomplete.• Maximum predictability achieved when both features areenabled.CDNLive 2007 Silicon Valley

RC Synthesis Flow With QoS Prediction EnabledCommands required to enable QoS Prediction are shown in orange.DEF.LEFcapTableRTL CompilerRead tech & physical libsRead source filesApply ConstraintsMap (PLE Driven)QoS PredictionSilicon VirtualPrototypingIncremental OptimizationGenerate ReportsGenerate Reportsset_attr lef_libraryset attr cap_table_fileset_attr def_filesynthesize –to_mappredict_qossynthesize –to_map -incrementalreport timing report powerreport areareport qorwrite_session write_set_loadwrite_encounterCDNLive 2007 Silicon Valley

How QoS Prediction Works (Part I)RTL Compiler 7.1Mapping (PLE driven)predict_qosgenerate files12write3.rcenc__(temp Linux dir)rc2enc.vrc2enc.sdcrc2enc.moderc2enc.defrc2enc.confrc2enc.tclrc2enc.enc_setup.tclreadSoC Encounter 6.2loadConfigdefInplaceDesigntimeDesign -preCTS4 extractRCrcOut ‐spefdefOut / saveNetlistreportTiming1. Map design to gates2. Generate files for Encounter. The predict_qos cmd generates the files SOCE requires as input.3. Files generated in step 2 are written to a temporary directory named .rc__4. Run Encounter in batch mode. rc2enc.tcl is sourced, causing the following commands to beexecuted:• Load the tech and physical libs, capacitance table and netlist• Read in the floorplan (macro and pin placement only)• Place the standard cells• Perform a trial route• Extract interconnect parasiticsCDNLive 2007 Silicon Valley

How QoS Prediction Works (Part II)RTL Compiler 7.1Mapping (PLE driven)predict_qosgenerate fileselaborateannotate loadsincremental opto 8Increment Opto(SPEF/PLE driven)679readread.rcenc__(temporary Linux dir)enc2rc.venc2rc.DEFenc2rc.SPEF5write4SoC Encounter 6.2loadConfigdefInplaceDesigntimeDesign -preCTSextractRCrcOut ‐spefdefOut / saveNetlistreportTiming5. Write out physical design info. After extraction is done, SOCE writes out the following files:Netlist (enc2rc.v), fully placed floorplan (enc2rc.DEF), net parasitic file (enc2rc.SPEF)6. RC removes the existing version of its design from memory, reads in the SOCE generatedversion and elaborates it.7. SPEF file is read and nets are annotated with actual delay based on placement.8. Incrementally optimize design9. ReoptimizeCDNLive 2007 Silicon Valley

Benchmark Testing

What was measured• Quality of Results (QoR) metrics– total negative slack (TNS)– worst negative slack (WNS)– Instance count– Area– Leakage Power– Dynamic Power• Synthesis methodology’s predictability– How accurately did the synthesis results match those from SOCEncounter?– Prediction was measured by comparing QoR metrics and netcapacitive loads after synthesis and after physicalimplementationCDNLive 2007 Silicon Valley

What Was Synthesized & Routed?The RTL source for the following two silicon proven designs weretaken through RTL Compiler and SOC Encounter (trial route).Design ADesign BBasic Function Network Switch Encoder/DecoderDesign Is Silicon Proven yes yesProcess Node 130nm 65nmMulti-Vt Library no noMulti-Supply Voltage no noCore Clock Period(s) (ps) 4500, 5500 3000Instance Count 170K 360KScan Flops Inserted Yes YesScan Flop Coverage 98% 96%RAMs 125 54CDNLive 2007 Silicon Valley

Benchmark Testing Methodology2TestcaseDesigns3X Synthesis =Strategies6 UniqueRC Netlists1 Back EndX =Flow6 RoutedDesignsDesign ARTLDesign BRTLRTL CompilerRC-PhysicalWLMSynthesisZero WLMSynthesisdesignB.rc.dwp.vgdesignA.rc.rcp.vgDesignB.DWP.sdcdesignA.rc.rcp.sdcDesignS.DWL.loaddesignA.rc.rcp.loadDesignS_DWP.rptsdesignA_rc.rcp.rptsdesignB.rc.wlm.vgDesignB.DWP.sdcdesignA.rc.wlm.vgDesignS.DWL.loadsesignA.rc.wlm.loadDesignS_DWP.rptsdesignA.rc.wlm.rptsdesignB.rc.zero.vgdesignA.rc.zero.vgDesignB.DWP.sdcdesignA.rc.zero.sdcDesignS.DWL.loaddesignA.rc.zero.loadDesignS_DWP.rptsdesignA_rc.zero.rptsSOCEncounterFloorplanCreated onceper design.Reused for eachP&R runPlace &RouteOptimizeDesigndesignB.soc.dwp.vgdesignS.soc.dwp.vgDesignB.DWP.sdcdesignS.soc.dwp.sdcDesignS.DWL.loaddesignS.soc.dwp.loadDesignS_DWP.rptsdesignS.sco.dwp.defdesignS_soc.dwp.rptsdesignB.soc.wlm.vgdesignS.soc.wlm.vgDesignB.DWP.sdcdesignS.soc.wlm.sdcDesignS.DWL.loaddesignS.soc.wlm.loadDesignS_DWP.rptsdesignS.soc.wlm.defdesignS_soc.wlm.rptsdesignB.soc.zero.vgdesignS.soc.zero.vgDesignB.DWP.sdcdesignS.soc.zero.sdcDesignS.DWL.loaddesignS.soc.zero.loadDesignS_DWP.rptsdesignS.soc.zero.defdesignS_soc.zero.rptsCDNLive 2007 Silicon Valley

Back End Flow For All Netlists.sdc.vg.libLEFcapTableSOC Encounter 6.2loadConfig.DEFdefInrcOut –set_loadset_loadplaceDesigndefOut.DEFtimeDesign -preCTSreport_constraintreport_powersummary_reportRPTsoptDesign ‐prectssavedesignCDNLive 2007 Silicon Valley

Measuring Predictability Using QoR MetricsRTL Compiler.vgrc.set_loadRC.rptMetric RC SOCTNS -1340 -1500WNS -1.01 0.95AreaLeakage PwrDynamic PwrSOC EncounterSOC.rptsoc.set_loadCDNLive 2007 Silicon Valley

Measuring Predictability Using Net LoadRTLCompiler.vgSOCEncounterrc.set_loadsoc.set_loadcompare_load.pl(Perl script)NetRCLoadSOCLoadDeltaNet A 0.033 0.030 0.003Net B 1.0 1.200 -0.2CDNLive 2007 Silicon Valley

WNS Measurements – Design AWorst Negative Slack (ps) - Design ASynthMethodologyRC SOC Variance (%)Zero -1765.9 -2612 -32.4WLM -878.6 -1719 -48.9RC-Physical -1309.2 -1503 -12.9SynthMethodologyMax Performance - Design ATarget ClockPeriod (ps)Max Clock Period(ps)Max Freq(Mhz)Zero 4500 7112 140.6WLM 4500 6219 160.8RC-Physical 4500 6003 166.6*Max clock period is calculated based on SOC WNSCDNLive 2007 Silicon Valley

WNS Measurements – Design BWorst Negative Slack (ps) - Design BSynthMethodologyRC SOC Variance (%)Zero 0 -1003 -100.0WLM 0.3 -997 -100.0RC-Physical -299.7 -336 -10.8SynthMethodologyMax Performance - Design BTarget ClockPeriod (ps)Max Clock Period(ps)Max Freq(Mhz)Zero 3000 4003 249.8WLM 3000 3997 250.2RC-Physical 3000 3336 299.8*Max clock period is calculated based on SOC WNSCDNLive 2007 Silicon Valley

Total Negative Slack MeasurementsSynthMethodologyTotal Negative Slack - Design ARC SOC Variance (%)Zero -1,429,286 -9,270,300 -84.58WLM -682,038 -5,216,300 -86.92RC-Physical -1,121,632 -1,546,500 -27.47SynthMethodologyTotal Negative Slack - Design BRC SOC Variance (%)Zero 0 -7,204,400 -100.00WLM 0 -844,137 -100.00RC-Physical -185,181 -137,606 34.57CDNLive 2007 Silicon Valley

Instance Count MeasurementsSynthMethodologyInstance Count - Design ARC SOC Variance (%)Zero 192,682 242,353 -20.50WLM 188,389 239,057 -21.19RC-Physical 190,131 226,254 -15.97SynthMethodologyInstance Count - Design BRC SOC Variance (%)Zero 398,143 450,808 -11.68WLM 387,215 438,414 -11.68RC-Physical 429,934 429,250 0.16CDNLive 2007 Silicon Valley

Area MeasurementsSynthMethodologyArea - Design ARC SOC Variance (%)Zero 35,034,968 35,555,027 -1.5WLM 34,989,550 35,521,032 -1.5RC-Physical 35,858,842 35,498,556 1.0SynthMethodologyArea - Design BRC SOC Variance (%)Zero 5,708,741 6,258,129 -8.8WLM 5,686,524 6,162,961 -7.7RC-Physical 6,449,804 6,148,593 4.9CDNLive 2007 Silicon Valley

Leakage MeasurementsSynthMethodologyLeakage Current (nW) - Design ARC SOC Variance (%)Zero 2,897,507 3,067,821 -5.55WLM 2,870,407 3,042,765 -5.66RC-Physical 3,177,894 3,149,049 0.92SynthMethodologyLeakage Current (nW) - Design BRC SOC Variance (%)Zero 21,494,055 23,689,264 -9.27WLM 21,348,786 27,438,608 -22.19RC-Physical 23,497,194 23,965,839 -1.96CDNLive 2007 Silicon Valley

Dynamic Power MeasurementsDynamic Power (nW) – Design ASynthMethodologyRC SOC Variation (%)Zero 705,876,554 770,393,478 -8.37WLM 702,497,998 764,619,809 -8.12RC-Physical 728,521,983 710,065,116 2.60SynthMethodologyDynamic Power (nW) – Design BRC SOC Variation (%)Zero 166,698,734 461,485,386 -63.88WLM 164,720,532 480,983,077 -65.75RC-Physical 229,548,980 469,328,523 -51.09CDNLive 2007 Silicon Valley

Create set_load HistogramsNetRCLoadSOCLoadDeltaNet A 0.033 0.030 0.003Net B 1.0 1.0 0Sort nets basedon the cap loaddeltaHistogram Bin(pf)# of NetsLess than -1 5-0.999 -0.900 2-0.899 -0.800 4Net C -0.3 0.5 -0.8Net D 1.3 1.3 0Net E 1.2 2.6 -1.4RC vs SOC set_loadComparison Results-0.099 0 1000.001 0.099 500.100 0.199 10Greater than +1 4Histogram DataCDNLive 2007 Silicon Valley

Analyzing set_load HistogramsCDNLive 2007 Silicon Valley

Analyzing set_load Histograms(sample histogram for illustration purposes only)Red & green graphs are centered around a delta of ‐0.0068pf and has a very wide distribution.Blue graph is centered around a delta of 0and the distribution is narrow.CDNLive 2007 Silicon Valley

Net Load Correlation – Design APerfect CorrelationRC set_loadoptimistic comparedto SOCRC set_load pessimisticcompared to SOCCDNLive 2007 Silicon Valley

Net Load Correlation – Design BPerfect CorrelationRC set_loadoptimistic comparedto SOCRC set_load pessimisticcompared to SOCCDNLive 2007 Silicon Valley

QoR Metric Variation SummaryDesign B RC vs. SOC Variation (%)Synthesis Methodology WLM ZWLM RC‐PhysicalWNS -100.0 -100.00 -10.80TNS -100.00 -100.00 34.57Instance Count -11.68 -11.68 0.16Area -8.80 -7.70 4.90Leakage Power -9.27 -22.19 -1.96Dynamic Power -63.88 -65.75 -51.09CDNLive 2007 Silicon Valley

QoR Data Analysis• When examining each testcase design AFTER trial route &optDesign:– RC-Physical produced designs are consistently smaller, faster andconsume less leakage current– The dynamic power number for Design B was the only metric RC-Physical didn’t produce better results for. Since no switching activity filewas used to calculate dynamic power, the power numbers are likelyinaccurate. It is reasonable to expect actual dynamic powerconsumption to track the area and instance count trends• When examining the variation in RC QoR data vs SOC QoRdata:– RC-Physical produced far more predictable results than WLM and ZWLMmethodologies– RC-Physical WNS was within 13% of SOC– RC-Physical TNS was within 35% of SOC– RC-Physical instance count was within 16% of SOC– RC-Physical area & leakage were within 5% of SOCCDNLive 2007 Silicon Valley

Net Load Histogram Analysis• RC-Physical net load histograms were more closely centeredaround 0 (which is the indicator of perfect correlation).• Histogram distribution of RC-Physical net load values wasmore tightly spread around center.• WLM and ZWLM histograms showed far larger distributionbands and results between Design A & B were much lessconsistent.CDNLive 2007 Silicon Valley

Conclusion• RC-Physical benefits the logic design engineer by generatingsynthesis results that are significantly closer to their finalnumbers than what WLM or ZWLM can produce. Logicdesigners can have a higher degree of confidence that theresults they see in synthesis will hold through place and route.• RC-Physical benefits the physical design engineer by creatinga netlist that is a better starting point than the WLM or ZWLMnetlists. A better start point means timing closure is achievedwith less engineering effort and fewer iterations.CDNLive 2007 Silicon Valley

September 25, 2007Cadence Confidential: CadenceInternal Use OnlyCDNLive 2007 Silicon Valley 45