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2Chip Scale Review May/June 2011 [ChipScaleReview.com]

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4Chip Scale Review May/June 2011 [ChipScaleReview.com]

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EDITOR'S OUTLOOKGetting the Cooling to Where it’s NeededBy Ron Edgar [Technical Editor, Chip Scale Review]Not long before the demise ofDigital Equipment Corporation(DEC), they spent a fortunedeveloping an ill-fated water-cooledsystem, Aquarius. The loss, reputed to bein the order of $2B, no doubt contributedto their fall. However, it highlighted thewell-known fact that one of the mostserious problems facing system designers,and especially chip designers, is the realityof handling heat production. All but themost exotic of hardware has been, untilrecently, air cooled. Now, even my computeris water cooled. But standard techniquesare not enough for tomorrow’s needs _they are not getting close enough todissipate heat where it is produced. Hotspots are part of the problem, 3D stackingis another. Clock rates continue to climb andhigher levels of integration are contemplated.So what are we doing about it?IBM has been getting a lot of presscoverage on their efforts to improvecooling. Back in ’09, they announced theirAquasar hot-water-cooled supercomputer.This joint IBM and ETH Zurich venturecooled the processors with warm water andextracted the surplus heat with heatexchangers. The harvested heat was thenused to heat the building, reducing overallpower consumption. At CeBIT 2011 inHanover, Germany, IBM talked about theirprogram and their test chips _ 3D stackswith cooling channels between layers.CMOSAIC is a four-year projectbetween IBM Research, ETH Zurich, andÉcole Polytechnique Federale deLausanne (EPFL), which examinescooling techniques needed to support 3Dchip architectures. Says Professor JohnThome, CMOSAIC project coordinator,“The CMOSAIC project is a genuineopportunity to contribute to therealisation of arguably the mostcomplicated system that mankind hasever assembled: a 3D stack of computerchips with a functionality per unit volumethat nearly parallels the functional densityof a human brain.”Cooling between the layers is not the onlyway to go. In a paper (Bakir MS, Huang G,Sekar D, King C. 3D Integrated Circuits:Liquid Cooling and Power Delivery. IETETech Rev 2009;26:407-16) authored byresearchers at Georgia Institute ofTechnology, Intel, and SanDisk, theydiscussed fluidic through-silicon vias (F-TSVs), which circulates fluid through thestack using special TSVs. This papercharacterized their approach as, “Unlikeprior work on microfluidic cooling of ICsthat require millimeter-sized and bulkyfluidic inlets/outlets to the microchannelheat sink, the proposed micropipe I/Os aremicroscale, wafer-level batch fabricated,area-array distributed, flip-chip compatibleand mechanically compliant.” Read the fullarticle at http://tr.ietejournals.org/text.asp?2009/26/6/407/57826.In a recent article in Journal of LowPower Electronics, Vol. 7, 1-12, 2011,Cyber-Physical Thermal Management of3D Multi-Core Cache-Processor Systemwith Microfluidic Cooling, Qian et al. notonly used microfluidic channels, butcoupled this with “a thermal managementthat can actively control the flow-rate ofmicrofluidic channels to maintain thesystem temperature within certaintemperature range.” By dynamicallychanging the flow rate to different partsof the system according to predictivesoftware, it “. . . attains a more eventemperature distribution with lowerpumping power overhead. The total flowrate,which is a direct reflection ofpumping power, has been reduced by upto 72.1% with a fine grained flow-ratecontrol.” Yes, another outstanding read.There are many other areas being lookedat to help with heat removal. One such isthe concept of very thin, liquid-cooled heatsinks. This would allow board pitch toshrink. Another is in the area of thermalinterface materials (TIMs). Because TIMsaccount for up to 50% of the thermalresistance, there is keen interest in thisarea. Hierarchical nested surface channels(HNCs) need to be optimized and are atradeoff between reduced bondlinethickness and increasing resistance withsmaller HNC cell sizes. For 3D stacks,underfill was originally used to reducemechanical stress. Now, thermal propertiesare also important. Epoxy containingdielectric particles such as SiO 2and AL 2O 3conventionally applied by capillary forcesresult in poor thermal properties, typicallyworse than most TIMs. However, atechnique called sequential underfillingfilters the underfill as it exits the stack andloads the space between the dice withmuch more dielectric material than theconventional method. This allows muchbetter thermal flow by putting the particlesin closer contact with the dice and eachother.Much of the material here comes fromIBM _ thank you. And what are othersdoing? Lots! Intel, AMD, and a host ofresearch facilities are hard at work hopingto keep Moore’s Law alive by getting thecooling to where it’s needed.8Chip Scale Review May/June 2011 [ChipScaleReview.com]?

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GUEST EDITORIAL3D: Progressing Past the PowerpointBy Françoise von Trapp, Contributing Editor [3D InCites]We’ve been hearing it a lot inthe past year: when will 3Dthrough silicon via (TSV)stacking move past the powerpoint to actualproduction? The implication that 3Dintegration using TSVs looks good in theory,but won’t ever make it to market adoptionhas been one of the ongoing debated topics.But it’s been a valid concern. As many reasonsas there are to move to 3D integration, therehave historically been just as manyarguments against it. Mostly, I’m compelledto surround myself with fellow Kool-aiddrinkers; those of us who see the eleganceand beauty in the 3D solution and don’t wantto see the roadblocks because they’re merelynuisances to those of us who truly believe.3D just makes sense, and sooner or latereveryone’s going to have to see what we see.And then those darn realists poke pins in thatbubble. It costs too much; there’s too muchneeded to motivate the changes to theexisting infrastructure; it doesn’t matter if itWORKS, it will sit on the shelf forever untilthere’s just no other way to do it. In mydarkest moments of pure skepticism, I’veeven voiced my theory that there are thosehigh-level decision makers in the industrywho prefer to coast along to their retirementwith existing technologies rather than rockthe boat with something disruptive.But in the past few months, things arehappening. The pessimists are comingaround. They’re willing to take the first steptowards adoption in the form of 2.5D siliconinterposer technologies (Figure 1). The 3Devangelists are also coming to the sameconclusions; they know their time will comeand at least 2.5D is a step in the rightdimension (pun intended). And suddenly,we’re there; moving beyond the powerpointpresentations to what Jan Vardaman,president and CEO of TechSearchInternational called “real engineering work.”She talked about this progress in herpresentation at the IMAPS Global BusinessCouncil, March 8, 2011. Vardaman pointedto progress in design tool developments;process improvements such as via fill, waferthinning and handling, and singulation; newinspection and failure analysis technology;reliability data; and standards establishment.Still needing work is design software, thermalmanagement, test, and reliability data.The Killer “Killer App”It’s well known that MEMS and CMOSimage sensors (CIS) opened the manufacturingdoor for via-last TSVs _ the first applicationsfor TSVs in 2.5D. For a while it was thoughtthat DRAM memory stacks would be thenext step in realizing 3D IC stacks with TSVs.Samsung and Elpida both announcedprototypes and Elpida went so far as to suggestproduction dates. Those well-known imagesbecame part of every 3D powerpoint asproof of 3D ICs potential. It was expectedthat memory on logic stacks would follow.And then somehow, the memory+logicapplication leapfrogged past DRAM aswide I/O DRAM on Logic was announcedas the “killer app” for 3D IC.Figure 1. 2.5D-IC moves existing chips and design methodologies into the third dimension with interposersor flip chips. (Source: Mentor Graphics)At the GSA Memory Conference: 3DArchitecture with Logic & MemoryIntegrated Solutions, March 31, 2011, Iasked the experts why; what happened toDRAM being the next “killer app” despiteall the roadmap declarations? According toDr. John Lau, Fellow of IndustrialTechnology Research Institute (ITRI)everyone predicted that DRAM TSV stackswould happen before passive siliconinterposers. “But everyone was WRONG!Passive interposers will be in productionbefore the memory chip,” He noted.“Whoever published that roadmap was 99%wrong.” He noted that since Elpida made itsannouncements, nothing has shipped.Moreover, he said Elpida didn’t even have apilot line for stacking memory chips. Cost,he says, is always most important.Kyowin Jin VP, Product Planning,Worldwide Marketing & Sales, HynixSemiconductor, Inc. explained further thatwhile using TSVs in DRAM memory ismotivated by the technology benefits ratherthan cost, the benefits to DRAM stacksalone are not compelling enough. However,when you add in the benefits of stackingthat DRAM cube on a logic stack, itbecomes a worthwhile value proposition.Improving yield of “logic + stacked DRAMcombined” becomes more important thanimproving “DRAM only yield”, heexplained. According to Yuan Xie,Pennsylvania State University, for 3D ICto be adopted, it has to both enable novelarchitectures as well as identify a killer app.3D IC enables novel architectures such aslatency (fast interlayer interconnect),bandwidth (high number of connectionsbetween layers), heterogeneous integration,and a cost benefit. “Killer apps” includehigh-capacity memory, multi/many-coreprocessors, and exascale computing.Specifically, Xi noted that wide I/O DRAMdemonstrates the bandwidth benefits of 3Dfor future quad High-Definition TV(HDTV) applications.10Chip Scale Review May/June 2011 [ChipScaleReview.com]

What’s Now and What’s NextSupporters of Si interposer technologyhave been voicing the benefits of 2.5D forquite some time, but is wasn’t until Xilinxintroduced its stacked silicon technologyabout six months ago that technologistsbegan talking about it as not an alternativebut a the first step towards achieving full3D. Lau differentiates between 3D siliconintegration and 3D IC Integrations. 3D Siintegration is the furthest away frommarket adoption, and involves very highaspect ratio TSVs in ultra thin waferswithout bumping. He divides 3D ICintegration into 3D TSV memory stacks,active interposers for stacking DRAM onlogic, and passive interposers in 2.5 and3D configurations. Due to its ability toleverage existing infrastructure, Laupredicts that passive interposer technologywill be used the most in the next ten yearswhile the kinks are worked out of “true”3D IC integration. Active interposers withTSVs need an ecosystem, EDA tools andbusiness models. Ultimately, the way togo to compete with Moore’s law will be3D SI integration (Figure 2), and that theindustry should strike to make this happen.Realistically, were looking at 10 yearsbefore it’s in production.ConclusionSigns of movement beyond the powerpointare everywhere. Foundries and packaginghouses are gearing up to add what hasbeen dubbed “mid-end” processes forsilicon interposer and 3D processes.Amkor has been working with Xilinx andTSMC to assemble its stacked silicon FPGA.ASE is also promoting its 2.5D processes.On April 11 2011, TSMC threw its hat inthe mid-end process ring, announcing itwould expand its wafer bumping andwafer level packaging offerings, and beginfocusing on silicon interposer processes. OnApril 19, 2011, STATS ChipPAC announcingthe addition of a 300mm “mid-end”process flow to support the advancedmanufacturing requirements of 2.5D and3D TSV as well as wafer level packaging,flip chip and embedded die technology.Before we know it, these technologieswill be referenced in powerpoints onlyfor historical reference. In its place, lookfor developments of 3D Si integration.Figure 2. 3D si integration involves very shortwiring with TSVs between bonded ultrathin waferswithout bumps. (Source: ITRI)Chip Scale Review May/June 2011 [ChipScaleReview.com] 11

INDUSTRY NEWSIHS iSuppli Ranks SemiconductorSuppliers; Samsung closing in onIntelIn its recently released market researchreport for 2010, IHS iSuppli reports thatthe #2 ranked semiconductormanufacturer, Samsung, is closing the gapbetween it and Intel with a 9.2% marketshare of global chip revenue, up from7.6% in 2009. This puts the company only4.1 percentage points behind Intel. Evenmore interesting is the shift for companieslike Renesas, Micron and Broadcom, wholeapt several places ahead to put them inthe top 10 at 5, 8, and 10 respectively.ST Microelectronics slipped back from5th to 7th place, and Qualcomm alsodropped back from 6th to 9th place. Themost dramatic increase of revenue wasRenesas, with a 130% increase from$5153 to $11,893.“The rise of Samsung is one of thebiggest stories of the last decade in theworldwide semiconductor market,” saidIHS analyst Dale Ford. “When expertsdiscuss competition for Intel, they almostalways focus on Advanced Micro DevicesInc. (AMD). While it is true that AMD isIntel’s major competitor in themicroprocessing unit (MPU) market,Samsung is the primary rival of Intel foroverall semiconductor market share. Andalthough they are mainly indirectcompetitors in the marketplace, Intel andSamsung have been ranked No. 1 and No.2, respectively, for a number of years.”In 2001 Intel’s market share at 14.9% wasmore than three times that of Samsung at3.9%; Samsung ranked fifth then.IHS iSuppli analysts attribute Samsung’sgrowth to the surging IC memory marketand its position as the top supplier ofDRAM and NAND. Additionally, Thememory boom has also moved other majormemory suppliers up the market sharerankings and charts. Micron Technology,Hynix Semiconductor and Elpida Memoryexpanded their share of the total market by1.1%, 0.7% and 0.4%, respectively.Renesas’ impressive rise in revenuewas largely due to its merger with NEC2009Rank123497513614158111018171923162021222430292010Rank12345678910111213141516171819202122232425Company NameIntelSamsung ElectronicsToshibaTexas InstrumentsRenesas Electronics Corp.HynixSTMicroelectronicsMicron TechnologyQualcommBroadcomElpida MemoryAdvanced Micro DevicesInfineon TechnologiesSonyPanasonic CorporationFreescale SemiconductorNXPMarvell Technology GroupMediaTeknVidiaROHM SemiconductorFujitsu Semiconductor Ltd.Analog DevicesMaxim Integrated ProductsXilinxAll OthersTotal Semiconductor2009Revenue32,18717,49610,3199,6715,1536,2468,5104,2936,4094,2783,9485,2074,4564,4683,2433,4023,2402,5723,5512,8262,5862,5742,0911,6571,69978,11230,194Electronics. The two companies, whichhad combined revenues in 2009 of $9.5B,grew 24.7%, less than the overall market,to $11.9B in 2010.Japanese Earthquake Hits Supply ofCell Phone Image SensorsAccording to market research companyIHS iSuppli, the March 11 earthquake inJapan is impacting the production ofCMOS image sensors (CIS) at Toshiba’sIwate image sensor fab, which was shutdown, as well as delaying delivery of CISfrom Sony to cell phone OEMS.Together, the companies accounted for19.2% of the 2010 global handset digitalcamera image sensor revenue.“With their low cost and easyintegration with other electronics, CMOShas long been the technology of choicefor cell phone cameras,” said PamelaTufegdzic, analyst for consumer electronicsat IHS. “The Japan earthquake andsubsequent logistical challenges have2010Revenue40,39427,83413,01012,99411,89310,38010,3468,8767,2046,6826,4466,3456,3195,2244,9464,3574,0283,6333,5533,1963,1183,0902,8622,3672,31192,667304,075PercentChange25.5%59.1%26.1%34.4%130.8%66.2%21.6%106.8%12.4%56.2%63.3%21.9%41.8%16.9%52.5%28.1%24.3%41.3%0.1%13.1%20.6%20.0%36.9%42.8%36.0%18.6%32.1%Percentof Total13.3%9.2%4.3%4.3%3.9%3.4%3.4%2.9%2.4%2.2%2.1%2.1%2.1%1.7%1.6%1.4%1.3%1.2%1.2%1.1%1.0%1.0%0.9%0.8%0.8%30.5%100.0%CumulativePercent13.3%22.4%26.7%31.0%34.9%38.3%41.7%44.6%47.0%49.2%51.3%53.4%55.5%57.2%58.8%60.3%61.6%62.8%64.0%65.0%66.0%67.0%68.0%68.8%69.5%Table 1. IHS iSuppli Table: Final Worldwide Revenue Ranking for the Top-25 Semiconductor Suppliers in2010 (Ranking by Revenue in Millions of U.S. Dollars)disrupted a portion of the supply of thiskey component.”While CIS production and distributionhas been impacted, supplies of the majoralternative image sensor technology _CCDs _ appear to be unaffected in the nearterm. Because of their higher image quality,CCDs are commonly used in digital stillcameras. In contrast, CIS are predominatelyused in cell phones and often in otherdevices where the camera is secondary toother functions. The global CCD market isdominated by Japanese suppliers includingSony, Panasonic Corp., Fujifilm, SharpCorp. and Toshiba.CEA-Leti to Implement Multiple EVGroup Systems on its 300mm 3D LineCEA-Leti has installed multiple EVGtools in its 300mm cleanroom dedicatedto R&D and prototyping for 3D integrationapplications. Although this state-of-theartfacility is focused on R&D andprototyping, EVG’s equipment will12Chip Scale Review May/June 2011 [ChipScaleReview.com]

Figure 1. EVG850 production bonding system fordirect wafer bonding installed in Leti’s 300mm 3Dline. (Courtesy of Leti)reportedly be used in 3D technologydemonstrations for Leti’s global customerbase, as well as low-volume pilot productionon 300mm wafers with the end goal oftransferring the processes to their industrialpartners’ high-volume manufacturingenvironments.The EVG systems to be deployed onCEA-Leti’s new 300mm 3D line includean IQ Aligner production mask alignmentsystem, a SmartView NT highestprecision bond alignment system, anEVG560 production wafer bondingsystem and an EVG850 productionbonding system for direct wafer bonding(Figure 1). CEA-Leti intends to tapEVG's process know-how in 3Dintegration and through-silicon via (TSV)manufacturing, as the institute’s 3Dofferings include TSVs along withadvanced capabilities in alignment,bonding, thinning and interconnects.“These new tools offer important newcapabilities to Leti and our partners,” notedCEA-Leti CEO Laurent Malier. “Togetherwe will demonstrate 3D and heterogeneousintegration technologies on 300mm wafers.”SEMI CEO and President, StanMyers, to Step Down from ExecutiveLeadershipSEMI has announced the impendingretirement of CEO Stanley T. Myers,who has informed the SEMI InternationalBoard of Directors of his intention tostep back from executive leadershipthis year. Myers has participated formore than 50 years in the semiconductorindustry, including 24 years as a SEMIboard member, 15years as president andCEO of the association,as wellas chairman ofthe SEMI InternationalBoard in 1994.“Stan is a drivingforce at the helm ofour industry association,” said RickWallace, CEO of KLA-Tencor Corporationand Chairman of SEMI’s BOD. “Underhis leadership, SEMI has grown anddiversified to meet the changing needs ofmember companies that participate in oneof the world’s most complex andsophisticated high-tech industries. As Stananticipates the next chapter of his life, weappreciate his thoughtful and deliberateframework for a succession plan.”In consideration of Myers’ announcement,Wallace appointed a Board searchcommittee to evaluate candidate successorsfor the role that Myers will be vacating.Tim O’Shea, with the executive searchfirm Heidrick & Struggles, will conductthe search for SEMI. Myers plans tocontinue supporting the association whena new president and CEO is named.Crane Aerospace & Electronicsappoints John P DiStasio, SeniorDirector of Business Development,Microwave SolutionsCrane Aerospace & Electronicsannounced the appointment of John P.DiStasio, Senior Director of BusinessDevelopment forElectronics GroupMicrowave Solutions.DiStasio will lead theMicrowave Solutionsbusiness developmentteam, which includessites in Beverly, MA; Chandler, AZ; WestCaldwell, NJ; and San Jose, Costa Rica.Prior to his appointment, DiStasio heldthe position of Director of Field Sales atCobham _ M/A-COM, managing theworldwide field sales organization.DiStasio holds a BS in Electrical Engineeringfrom Northeastern University.Chip Scale Review May/June 2011 [ChipScaleReview.com] 13

Partnering to Enable Volume Manufacturing for 3D ICStacks with TSVsCollaboration between suppliers and semiconductor manufacturers is vital to helpensure that cost-effective processes are built into the R&D effort at the beginning.By Sitaram Arkalgud, Director of 3D Interconnect [SEMATECH]3D through silicon via (TSV) expertise to deliver innovative, manufacturable These include a lack of electronic designtechnology offers the benefits of process solutions.automation (EDA) tools, the need forfunctionality/performance Although SEMATECH has significantly cost-effective manufacturing equipmentenhancement and power/cost reduction broadened its charter to explore cuttingedgetechnologies and future-oriented reliability data involving thermal issues,and processes, insufficient yield andfor future semiconductor products.However, it demonstrates a classic manufacturing strategies, its approach to electromigration and thermo-mechanicalexample of the entry-level hurdles R&D is still rooted in the twin legacy of reliability, and compounded yield losses.facing the introduction of a new pulling important university research into Given the disruptive nature of TSVs, itstechnology. TSV is not a single the commercialization pipeline and working successful implementation will require antechnology element but spans all with equipment and materials suppliers unprecedented level of cooperationaspects of the industry. To successfully to ensure that the solutions it develops within the supply chain.enter high volume manufacturing (HVM), are both manufacturable and affordable. Issues that have restricted 3Dit requires broad collaboration among Today, especially given the increasing interconnects from entering HVMIDMs, equipment and materials suppliers, role suppliers are playing in technology encompass the front-end, assembly andfabless and fab-lite manufacturers, and development for the industry, SEMATECH packaging, and design and test. Timelytest, packaging and assembly companies.To encourages a new level of partnership in availability of advanced equipment is aaddress the various implementation which suppliers join as program members key enabler of 3D development. SEMATECHscenarios for 3D TSV, leading-edge in areas of specific expertise and interest, is working jointly with chipmakers,processes, integration approaches, share ideas and resources, and take equipment and materials suppliers, andmetrology technologies, and tool sets advantage of expanded opportunities to universities on device interactions formust be developed to deliver costeffective3D interconnect processes. Specifically, with new equipment and and future scaling to 30nm for planar anddevelop and test their tools and materials. fabrication at the 65nm node for planarSEMATECH traditionally focuses on materials suppliers now on board in its non-planar CMOS technologies. Thedeveloping materials and equipment 3D interconnect program, including result is a proven 3D TSV infrastructuresolutions to reduce cost-of-ownership NEXX Systems, Atotech, Tokyo Electron from materials through integration.(CoO). This is accomplished by working Ltd., and Lasertec, SEMATECH researchers A major supply chain question is whereto extend current technologies as long as are able to work on early development in the production line will TSVs bepossible and by preparing for transitions challenges including cost modeling, created _ as part of wafer fabrication, orto next-generation technology. Its track technology option narrowing, and at the end, as part of packaging? Therecord in preparing new technologies for technology development and benchmarking, answer affects both via processes and viamanufacturing include the industry’s while also building industry consensus on 3D. locations. It also determines who in the300mm wafer size transition, 193nmsupply chain does the job, wafer suppliersimmersion, and high-k and low-k materials. 3D Infrastructure Value Chain or packaging houses. Partnering withSEMATECH’s TSV research and 3D infrastructure and supply chain suppliers has allowed SEMATECH todevelopment is the successor to almost readiness is the biggest concern for the address these and other industry concerns.ten years of work the consortium has broad adoption of 3D ICs. A primary concern For example, SEMATECH has madeundertaken to develop robust copper/lowkinterconnect technology. SEMATECH’s roles are being questioned, resulting in 300mm 3D IC pilot line, with capabilitiesis that the traditional front-end and assembly considerable investment in a completeprogram on 3D integration focuses on avia-mid approach, with Cu _ questions regarding ownership, liability, in equipment, processing, and metrologyCu bonding and value proposition. In addition, there to advance 3D integration technologies.covering both die-to-wafer (D2W) and are various strategic technology choices SEMATECH members are now able towafer-to-wafer (W2W) integrations. It and different process steps that need to evaluate tools, process modules, and evenpartners with leading-edge equipment and be determined before the implementation integration sequences within a state-ofthe-artCMOS environment.materials suppliers and leverages their of 3D TSV interconnects is realized.14 Chip Scale Review May/June 2011 [ChipScaleReview.com]

One of the keys to fabricating many 3Dchip structures is the development ofhigh-yield, low-cost copper electroplatingsolutions that will enable high-density 3DTSVs. The technology of copperelectroplating provides a void-free fill forall feature sizes while minimizinginterconnect overburden and topographyat the same time. There is a variety ofproducts that may have different optimalfill conditions and working with supplierscan help researchers eliminate the variouschallenges associated with cost, newmaterials, and technical questions suchas copper pumping and overall reliability.Tool PartnersNEXX Systems, which manufacturersprocess equipment for advanced waferlevelpackaging (WLP), collaborates withSEMATECH on innovative electrodepositiontechnology in the area of advanced WLPitems and their participation in SEMATECH’s3D program provides valuable expertiseon developing robust, low-costelectroplating solutions. One advantageof the NEXX platform is the versatility ofthe tool, which allows the investigationof various methods and chemistries toachieve a reliable, consistent electrochemicaldeposition for wafer plating.Furthermore, the NEXX Stratus system(Figure 1) commonly used in thepackaging arena, is now being developedas a tool suitable for front-endcleanrooms. The inset (of Figure 1)shows the cross-section of copper filledTSVs plated using the NEXX Stratus.As a market leader in PCB and ICsubstrates industries, Atotech’sparticipation in SEMATECH’s 3Dprogram has been very valuable forSEMATECH engineers as they developprocess technologies for both D2W andW2W 3D applications. Atotech contributesto the R&D with cost-competitive,innovative chemistries and plating knowhow.The partnership has provided costeffectiveprocesses for industry-wideimplementation of copper electroplatingsolutions to enable void-free bottom-upfilling of high density 3D TSVs (Figure3). Specifically, the electrical characterizationdata and early reliability data generatedFigure 1. The NEXX Stratus system commonly used in thepackaging arena is now being developed as a tool suitablefor front-end cleanrooms. Inset shows the cross-section ofcopper filled TSVs plated using the NEXX Stratusfor the experiments enable the R&Dteams to analyze results and improve theprocess for best TSV performance.In addition to via size and shape,researchers must consider differentchemistries to form the vias potentiallyrequiring new etch chemistries. AsSEMATECH’s first associate member ofits 3D program, Tokyo Electron Limited(TEL) has provided their experience indeep silicon etching. TEL’s 300 mmTelius TM SP UD, the latest generationTSV etch tool, has allowed SEMATECHresearchers to investigate variousChip Scale Review May/June 2011 [ChipScaleReview.com] 15

Figure 2. Tokyo Electron’s Telius TM SP UD, and insetshows the details of a 5x50 micron TSVFigure 3. Atotech’s and SEMATECH’s partnershipenables cost-effective processes for industry-wideimplementation of copper electroplating solutions toenable void-free bottom-up filling of high density 3Dthrough-silicon-vias (TSVs)In 2010, Lasertec joined SEMATECHto further investigate and compare 3DTSV depth metrology schemes _ criticalwork necessary not only for TSV RIEprocess control, but also for providingcritical feed forward data for waferthinning and TSV expose processes.To facilitate this work, Lasertec placeda 300mm TSV infrared (IR) etchmetrology tool (Figure 4) inSEMATECH’s 3D R&D center, providingadvanced measurement capabilities thathave enabled accurate, repeatable TSVdepth measurements over a range of TSVdimensions (Figure 5).StandardsAlthough supplier engagement isimportant to deliver 3D TSV solutionsfor HVM, bringing in all players fromacross the entire industry _ fabless, fabliteand IDM companies, outsourcedassembly and test suppliers, and toolvendors _ is equally important to driveindustry consensus on integrationapproaches, process architectures, toolsets, creating a roadmap, and for standards.3D must accommodate the wide rangeof process parameters demanded bycompeting companies trying to establishtheir own proprietary process flows.Standards will be needed to ensurecommon interfaces from differentsuppliers. Heterogeneous stacking willrequire integrating processes fromdifferent manufacturers.SEMATECH is playing a strategic rolein working with the industry to drivemanufacturability and forge consensus ontechnology options, standards, and costmodeling. SEMATECH, the SIA,and SRC established the 3DEnablement Center targetingstandards in inspection, metrology,microbumping, bonding, and thinwafer and die handling.The center aims to solve key industryinfrastructure gaps includingdeveloping uniform standards and abetter understanding of keymanufacturing parameters, whichwould identify the key areas forConclusionThe technology roadmap requiresintense collaboration throughout theindustry supply chain. Design enablementcompanies, equipment and materialssuppliers, fabless, fab-lite, and assemblyand packaging companies must join withvertically integrated chipmakers todevelop system-wide solutions.Since 3D TSVs are destined to play sucha significant role in the products that applythem, partnering with the right supplier canmake the difference between success andobsolescence. The benefit with theSEMATECH/supplier partnerships ishaving ready and early access to advancedtechnology and the expertise in materialresearch, design, bonding, packaging andtesting. The result is a proven 3D TSVinfrastructure from design to testedpackage and the key to building theproducts that shape the market.chemistries to etch vias ranging from sub1μm to > 10μm in diameter, using a non-Bosch etch. Furthermore, the integrationof TEL’s 3D tools has enabledSEMATECH to explore different etchchemistries and develop an optimized etchprocess for TSVs. Figure 2 shows TokyoElectron’s Telius TM SP UD, and insetshows the cross section of a 5x50μm TSV.The partnership is a twofold benefit _refining TSV etch development processesand providing useful data to SEMATECHFigure 4. Lasertec’s WASVI series TSV300-IRmembers as well as TEL’s customers, andprovides advanced measurement capabilities thathas expanded from TSV etch developmenthave enabled accurate, repeatable TSV depthmeasurements over a range of TSV dimensionsto developing new technologies usedelsewhere in TSV processing.To effectively explore innovativemetrology capabilities that will make3D TSVs commercially viable,researchers from SEMATECH areexploring 3D metrology techniques tocomplement bonding tool development.The key steps towards bridging highvolumemanufacturing readiness gaps foran integrated 3D TSV tool platform anddeveloping metrology techniques thatwill accelerate adoption of 3D integration developing design tools to beFigure 5. The data in the graph above, from Lasertec’s WASVIis to partner with suppliers who help transitioned to mainstream highvolumeproduction.measurements made on 1 and 5 micron wide, dense andTSV300-IR tool, shows the repeatability of depthdevelop robust, cost-effective processmetrology solutions.isolated TSVs16 Chip Scale Review May/June 2011 [ChipScaleReview.com]

Chip-Level Spot CoolingBy Kaveh Azar, Ph.D. [Advanced Thermal Solutions, Inc.]As device densities and clockfrequencies continue toincrease, the switchingcurrents carried by the power and groundnetworks increase as well, leading to apower density increase. This increase,along with the lower power supplyvoltages and thinner wires, can adverselyaffect the robustness of an IC. Powerdistribution systems are designed toprovide needed voltages and currents tothe transistors that perform the logicfunctions of a chip. The supply voltagesare assumed to be constant across a chip,and are expected to operate reliably overthe chip’s lifetime. The complexity ofpower distribution systems and theirsubsequent spot heating have a significantimpact on chip performance. If ICdesigners do not consider such matters,they will have a difficult time producinga robust system since the chip may fail inthe field after it is embedded in a system.This issue is acutely highlighted by theInternational Technology Roadmap forSemiconductors (ITRS). Table 1 showstheir predicted trends in electronicspackaging for the coming years.As observed by Lin, et al., the projectedallowable maximum power density(shown in Table 1) is approachingYear of ProductionSupply Voltage (V)1Transistor (M)2Size (mm 2 )3Lg (nm)4Id.sat (uA/um)5Isd, leakage (uA/um)6Intrinsic Delay, τ (ps)7Switching Energy (fJ)8Max, P.D.(W/cm 2 )20130.944243101322200.110.250.019863.8720160.88848310927130.110.150.009163.8720190.717696310627440.110.100.003663.87Table 1. High Performance Double Gate LogicTechnology Trend Targets. [1]1Functions per chip at production (million transistors)2Chip size at production (mm 2 )3Physical gate length (nm)4Effective saturation drive current (uA/um)5Source/drain sub-threshold off-state leakage current(uA/um)6Intrinsic transistor delay for NMOS devices at 25 o C (ps)7Energy per device switching transition withdimensions W/Lg=3 (fJ/device)8Maximum allowable average power density (W/cm 2 )saturation in the next few years due tothe limited capability for system levelheat removal. 1 While increasing the chipsize can reduce the overall heat flux, thedesire to place more circuitry on the samesilicon will negate the notion of a largerchip. As noted by Taur, thermal problemsare amplified because the leakage current(power at the transistor level) forms themajor portion of the total powerdissipated by the chip. 3 Seeing as thisleakage is undesirable from the thermalstandpoint, it has become the primaryfactor in limiting the scaling of CMOSdevices.Due to the increase in powerdissipation across chips, local hot spotshave become a challenge for devicedesigners and thermal engineers. Fromthe combination of small device featuresand passage of electrical current in suchlocations, local heat flux densities haverisen dramatically while posing asignificant challenge for cooling thermalspikes on the chip. Figure 1 shows onesuch effect where there is significantpower and subsequently temperaturedistribution on the chip. 4The power profile over the chip haspeaks and valleys. The peaks representthe highest power concentration (largestheat flux, W/mm 2 ) and highestFigure 1. Map of FET Junction Temperature for a 115 WPackaged Power 4 Chip Derived from Chip PowerAnalysis (left) and Thermal Modeling Simulation (right). 4Figure 2. Power and Temperature Distributions at theCPU Junction. 5temperature levels on the chip. This isdepicted in Figure 2 for a CPU. Thesepeaks have a proportionally highertemperature than the rest of the chip andrepresent the potential for a chip’smalfunction or its catastrophic failure.Once we translate this to a PCB, some ofthe components are of high to averagepower and some are of low to averagepower. Consequently, the PCB has thesame power and thermal response as thechips on the components forming thePCB. This impacts the thermal responseof the components residing on it, i.e.,change of boundary conditions. Thethermal management at both levels ofpackaging: chip (component) and PCBare huge bottlenecks in the successfullaunch of an application. They becomeeven more prevalent as the heat fluxdensity increases.Despite significant advances incomponent packaging and materialdesign, the industry continues to strugglewith this issue. The solution for the spotcooling has two broad forms _ at thesilicon level and at the packaging level.Silicon LevelMany solutions have been explored atthe silicon level. Among these is thedeployment of micro-channel heatexchangers (MCHEs), thin-film thermoelectric coolers (TECs), micro heatpipes, and localized copper bumps toimprove heat spreading on a largersurface area, or in the case of an MCHE,transporting it to a different location.Figure 3 shows a stacked MCHE that isused for cooling a silicon substrate.The success of these techniques(except for a handful of highlycustomized applications, such as largerscale computers) has been weak andunsatisfactory. TECs, bumps, micro heatpipes, etc, have had moderate successin dampening the peaks observed as aresult of the power density variation.Often, because of the aspect ratio or thearea, the heat flux exceeds 400-500 W/Chip Scale Review May/June 2011 [ChipScaleReview.com] 17

Figure 3. Stacked Micro-Channel HeatExchanger for Substrate Cooling. 6cm 2 . In some high-power applications, itexceeds 1-2 kW/cm 2 . With such high heatfluxes, one can appreciate the limits ofthe aforementioned technologies.A notable approach to this problem hasbeen the electrical control of the chip.Dynamic thermal management(DTM)has been examined as a technique forcontrolling CPU power dissipation. DTMrefers to a range of possible hardware andsoftware strategies that work dynamically,at run-time, to control a chip’s operatingtemperature. 7Traditionally, the packaging and fansfor a CPU or computer system aredesigned to maintain a safe operatingtemperature even when the chip isdissipating the maximum power possiblefor a sustained period of time, andtherefore generating the highest amountof thermal energy. This worst-casethermal scenario is highly unlikely,however, and thus such worst-casepackaging is often expensive overkill.DTM allows packaging engineers todesign systems for a target sustainedthermal value that is much closer toaverage-case for-real benchmarks. If aparticular workload operates above thispoint for sustained periods, a DTMresponse will work to reduce chiptemperature. In essence, DTM allowsdesigners to focus on average thermalconditions in their designs, rather thanworst-case conditions.The key goals of DTM can be statedas follows:1. to provide inexpensive hardware orsoftware responses,2. to reliably reduce power and,3. to impact performance as little as possible.To better understand the process, themaximum power dissipation occurs whenall of the structures within the processorare active with maximum switchingactivity. In reality, the maximum powerFigure 4. Block Diagram and the Topical TemperatureMeasurement of a 10 x 10 mm Test Chip, respectively. 12dissipation is constrained by the softwareprogram that can maximize the usage andswitching activity of the hardware.Special max-power benchmarks can bewritten to maximize the switching activityof the processor. These benchmarks areoften quite esoteric, perform nomeaningful computation, and dissipatehigher power than ‘real’ programs. Thus,DTM techniques could be used solely totarget power levels seen in maximumpower benchmarks and would rarely beinvoked during the course of typicalapplications. 8Package LevelAt the package level, cooling solutionscan be applied to the top of the silicon,or alternatively the component isimmersed in some sort of heat transferfluid. The goal of these approaches is torapidly remove the heat from the deviceor to provide a medium that can effectivelyabsorb the thermal peaks by improvedthermal spreading. A number of techniqueshave been explored by many researchersin the field with varied success. 9 Table 2presents such techniques and theirrespective characteristics.Technology AdvantagesFan sinks with Compact,heat pipe (hybrid) versatileThermoelectricLiquid coolingDirect immersionRefrigerationCryogenicsSpot coolingHigh surfaceheat transferHighcapacitySub-ambientSuper coolingDisadvantagesReliability,space, limitedto ambienttemperatureReliability,low capacitySealing, cost,maintenance,packagingCost, sealing,packagingCost, power,space, packagingCost, power,packagingTable 2. Thermal and Deployment Characteristicsof Select Cooling Options. 9Other cooling solutions have beendeployed or exist at university orcompany laboratories. 10,11 One paper byLin and Banerjee demonstrates the impactof global and local cooling solutionsapplied to hot spots on dies specificallydesigned for such study. 12Figures 4a and 4b show the functionalblock layout of a test chip showing thepower density associated with each block.Nominal total power consumption is 90W. Figure 4b shows four hot-spots on thetopical substrate temperature profile ofthe test chip. In this case, the highesttemperature is around 73 o C.Figures 5a and 5b show the topicalsubstrate temperature profile of the testchip for global and spot coolingrespectively. The substrate temperatureprofile shows several hot spots, and thehighest junction temperature is around73 o C. Although the results shown here arespecific to the aforementioned IC, theconclusions drawn are more generic.Figure 5 shows the effect of applyingglobal and localized cooling strategies onhot spot management. As shown inFigure 5a, a lower junction-to-ambientthermal resistance (θ ja) obtained byapplying global cooling (through betterinterface material, higher coolingefficiency, etc.) reduces the maximumjunction temperature. However, on-chiphot spots and thermal gradients stillremain. On the other hand, localizedcooling solutions such as local spraycooling and thin-film thermoelectriccoolers can be applied to eliminate thehot spots. For example, if a thin-filmthermoelectric cooler is placed on thebackside of the wafer below the locationof the bottom-right hot spot, it caneffectively eliminate the targeted hot spotas shown in Figure 5b.SummaryThe power profile over the chip haspeaks and valleys. The peaks representthe highest power concentration (largestheat flux, W/mm 2 ) and highesttemperature levels on the chip. Thermalmanagement of these hot spots hasbecome a unique challenge for devicedesigners and thermal engineers alike.Through the combination of smallerdevice features and the passage of18Chip Scale Review May/June 2011 [ChipScaleReview.com]

Figure 5. Topical Temperature Difference for Global (5a) and Spot Cooling (5b) ofa 10 x 10 mm Test Chip. 12electrical current in such locations, local heat flux densities haverisen dramatically. They pose a significant challenge for coolingthermal spikes on the chip.It is clear that topical or spot approaches for the thermalmanagement of these hot spots are not sufficient. To successfullydevelop such products, it is essential for thermal managementand logic-flow to be considered concurrently, and for a systemlevel approach to be taken.References1. International Technology Roadmap for Semiconductors(ITRS). www.itrs.net.2. Lin, S. and Banerjee, K., Cool Chips: Opportunities andImplications for Power and Thermal Management, IEEETransactions On Electron Devices, Vol. 55, No. 1, January 2008.3. Taur, Y., CMOS Design Near the Limit of Scaling, IBM J.Res. Develop., Vol. 46, No. 2/3, 2002.4. Warnock, J., Keaty, J., Petrovick, J., Clabes, J., Kircher, C.,Krauter, B., Restle, P., Zoric, B. and Anderson, C., The Circuitand Physical Design of the POWER4 Microprocessor, IBMJournal of Research and Development, Vol. 46, No. 1, 2002.5. Wei, J., Thermal Management of Fujitsu’s High-PerformanceServers, Fujitsu Sci. Tech. J., 43, January 2007.6. Web Reference: http://plaza.ufl.edu/rxiong/research/STflow_files/micro-channels.JPG7, 8. Brooks, D. and Martonosi, M., Dynamic ThermalManagement for High-Performance Microprocessors, Proceedingsof the 7th International Symposium on High-PerformanceComputer Architecture, Monterrey, Mexico, January 2001.9. Azar, K., Advanced Cooling Concepts and Their Challenges,Presented at the Int. Workshop Thermal Investigations ICs andSystems (THERMINIC), Madrid, Spain, 2002.10. Rodgers, P., Eveloy, V., and Pecht, M., Limits of Air-Cooling:Status and Challenges, Proc. SEMI-THERM, 2005.11. Prasher, R., Chang, J., Sauciuc, I., Narasimhan, S., Chau, D.,Chrysler, G., Myers, A., Prstic, S., and Hu, C., Nano and MicroTechnology-Based Next-Generation Package-Level CoolingSolutions, Intel Technol. J., Vol. 9, No. 4, November 2005.12. Lin, S. and Banerjee, K., IEEE Transactions on ElectronDevices, Vol. 55, No. 1, January 2008.KAVEH AZAR, Ph.D., is the President and CEO of AdvancedThermal Solutions, Inc. (ATS). He may be contacted at 89-27Access Rd., Norwood, MA 02062, 1-781-769-2800; E-mailKazar@qats.com.Chip Scale Review May/June 2011 [ChipScaleReview.com] 19

3D Wafer Level Chip Scale Packaging: A SteppingStone to Full 3D IntegrationBy Daniel F. Baldwin, Ph.D., Paul Houston, Brian Lewis, Tim Sparks, Fei Xie [ENGENT, Inc.]Back-end-of-line (BEOL) existing infrastructures of WLP and highvolumeflip chip assembly. It will brieflyassembly involving 3Dintegration at the wafer level review 3D integration technologies, presenthas received increasing exposure in implementation strategies for 3D die levelelectronics literature. Development efforts integration packaging, and presentfor 3D wafer-level integration are examples of 3D die level integratedunderway worldwide, with the promise packaging solutions. Additionally, thethat this elegant integration technique will assembly advancements associated withenable a long-term solution to the and implemented to produce the 3D faceto-faceflip-chip-on-wafer (F2FFCoW)industry’s expanding computational powerand memory requirements. In the short package will be explained.term, however, a need exists for achievingmany of 3D integration’s benefits without 3D Die Level Integrationrequiring a vertically integrated production 3D die level integration is a device-levelinfrastructure typically needed for the full integration scheme wherein multiple layers3D wafer-level integration solution. of planar devices are stacked andFor emerging applications, there is a 3D interconnected in the Z-direction usingintegration technology that provides many various combinations of flip chipof the 3D wafer-level integration benefits interconnect, direct die bonding, andand leverages existing high volume BEOL through die vias. 3D die stacking is achievedproduction infrastructure. An initial by producing devices of a specific functionstepping stone for 3D integration is 3D dieto-wafer(D2W)or die-to-die (D2D) DRAM, embedded wireless networks, etc.)(i.e., embedded processors, DSPs, SRAM,integration. 3D integration at the die level that are bonded together in singulated oroffers key features like very high levels of tile form. Singulated known good dieintegration, very small form factor (KGD) are then vertically interconnectedpackages (often chip scale in size), very to create an integrated functional device.low profile packages, low weight 3D die level integration represents apackages, and improved digital and RF unique opportunity to gain the performanceperformance.and form factor advantages of 3D wafer3D D2W integration can be achieved via level integration without the drawbacks. 3Dface-to-face bonding of fine-pitch flip chip die level integration does not suffer fromcomponents and low - profile passives onto high yield loss due to good die being bondeda redistribution layer of another silicon to bad die during wafer integration, andcomponent - a wafer level chip scale does not require full-scale wafer processing.package (WLCSP). In this manner, a flip 3D wafer-level integration requires both,chip driver can be mounted directly onto a resulting in prohibitively high costs forCSP memory component, ASIC, etc. Wafer integrated packaging solutions for highperformanceapplications. In theselevel packaging (WLP) provides a highlyfunctional platform from which to applications, 3D wafer bonding isimplement a new package technology supplanted by D2W or D2D bondingincorporating 3D D2W integration. because of its ability to assemble onlyMoreover, such a packaging architecture probed good die, to support easierprovides a cost-effective, rapid time-tomarketalternative to emerging 3D wafer-dissimilar sizes, to interconnect die fromalignment tolerances, to interconnect die oflevel integration technologies.dissimilar size wafers, and to interconnectThis article summarizes this low-cost, 3D die of dissimilar base semi-conductorWLCSP technology that leverages the materials _ i.e., heterogeneous integration. Figure 1. 3D WLCSP and FC Process Flow [6]20 Chip Scale Review May/June 2011 [ChipScaleReview.com]Implementation strategies for 3DDie-Level IntegrationThere are a number of techniques thatcan be used to implement 3D die-levelintegration. These include D2D integration,D2W integration, die to interposerintegration, and combinations thereof. Thekey to implementing high performance andhigh reliability 3D integrated die packagesis to leverage existing domesticinfrastructure, interconnect structures thathave a proven reliability track record, andwell-characterized packaging architectures.Fundamental building blocks to 3Dintegrated die packages are multi-layer,wafer-level redistribution technology,integrated passive structures, embedded ICstructures, very fine pitch flip chip/directdie bonding, through silicon/substrate vias,wafer/die thinning, and warpagecompensation of thin die and substrates.In most instances, die-level integrationleverages industry-proven wafer-levelredistribution technologies for whichthere is a strong domestic manufacturinginfrastructure. This follows since mostICs are designed for wirebonding and toa lesser extent flip chip, and the formerdoes not lend itself well to 3D integration.

BEOL redistribution processing providesthe interconnect structure which ensuresa compatible I/O pad structure betweenthe ICs during 3D bonding. Figure 1shows an example of one such 3D dielevel implementation using redistributiontechnology.Proven techniques for interconnecting 3Ddie stacks include wirebonding and bumpbonding such as solder flip chip, thermosonicbonding, thermocompression bonding, andlow-temperature compression bonding.Additional, more involved, techniques for 3Ddie interconnect include silicon fusionbonding, polymer bonding, metal-to-metalfusion (e.g., Cu to Cu) bonding, direct bondinterconnect TM (DBI), and eutectic bonding.These later techniques are more common inwafer bonding applications but can be usedfor D2W and D2D bonding. The choice ofwhich interconnect structure or combinationof interconnect structures depends onsemiconductor type, form factor requirements,and electrical performance requirements. Thegood news is that 3D die-level integration canaccommodate many interconnect variationswithin a package giving the designer flexibilityin the cost/performance tradeoff.When thickness profile is less of aconstraint, interconnect interposers with andwithout through silicon vias (TSVs) can beimplemented. Often the interposers are Sibased,taking advantage of the widelyavailable, domestic 150mm and 200mmsilicon foundry infrastructure. Thisinfrastructure is finding new life in producingvery high density and cost effective 2D and3D interposers.Figure 2 shows a highly integrated, chipsize,four-die module based on D2Dintegration and wafer-level redistributiontechnology with a maximum packagethickness of 0.8mm. Figure 2b shows thepackage stack-up and Figure 2a shows the4 die module without the high densitymultilayer substrate. Die 1 is a large memorydevice that serves as the base die for 3Dintegration. It is redistributed to incorporatea multilayer, polymer dielectric/Cuinterconnect structure to receive Die 2, 3,and 4 in a flip chip configuration. A highdensity,microvia substrate is precisionbonded to the top sides of Die 2, 3 and 4. Auwire ball bonding is then used to interconnectthe high-density substrate to theredistribution pads of Die 1 (Figure 2e).Next the package is encapsulated and thehigh density substrate CSP pads are solderballed to complete the package assembly(Figure 2d).Die-to-interposer integration is anotherinnovative way to achieve 3D D2D/D2W.Figure 3 shows a cross-section of a highspeedRF module with eight heterogeneousdie (4 GaAs, 2 SiGe, 2 Si) flip chip bondedto an integrated TSV Si interposer substrate.Three different flip chip interconnects areused at the first level including coppercolumn-solder interconnects, noble metal,plated stud-solder interconnects, andcontrolled collapse solder interconnects.Figure 3 illustrates a copper column-solderflip chip interconnect between a high speedGaAs RF device and TSV interposer as wellas the solder flip chip interconnect betweenthe TSV interposer and the high densityorganic substrate. This module includes flipchip pitches down to 150mm, high-densityChip Scale Review May/June 2011 [ChipScaleReview.com] 21

wafer-level redistribution interconnects on the interposer, thinned GaAs die downto 100mm thick, surface mount passives, thin-film passives, 100mm underfillkeep-out areas, and 200mm spacing between die requiring precision underfillprocessing.Figure 4 shows an example of a qualified 3D D2W integrationtechnology utilizing very-fine-pitch flip chip, wafer-level redistribution,and wafer-level balling technologies. This packaging scheme involvesmounting a flip chip component to the active surface of a WLCSP, enabling3D die-level integration. This packaging scheme has been successfullydemonstrated in an assortment of applications including the MEMS-ASICcombination highlighted in reference 5.This implementation of 3D die-level integration is realized by face-to-facebonding of fine-pitch flip chip components down to 80μm pitch (ACT die)onto a redistribution layer of the base WLCSP (PA wafer). In this manner forexample, a flip chip driver can be mounted directly onto a memory component,ASIC, driver chip, etc. This new low-cost 3D WLCSP technology leveragesFigure 2. High Speed Digital Module with Die to Die Integration ¨C 2 the existing infrastructures of WLP and high volume flip chip assembly. WLPProcessors and ASIC to Memoryprovides a highly functional platform from which to implement the new packagetechnology incorporating 3D D2W integration. Moreover, such a packagingarchitecture provides a cost-effective, rapid time-to-market alternative toemerging 3D wafer-level integration technologies.The 3D-WLCSP is a qualified package (first and second level interconnects)in volume production. Efforts have focused on wafer level processing andvery-fine pitch-flip chip placement forming the 3D-WLCSP and the associatedchallenges that this type of packaging and assembly includes. Key aspects ofwafer level processing have been explored including wafer level redistribution,ball drop, wafer thinning, dicing thinned wafers, and flip chip bumping.Moreover, flip chip pitch and bump size has been varied, as well as key assemblymaterials (including fluxes and underfills) used to attach the flip chip to theWLCSP. Process solutions for flip chip fluxing methods for very-fine-pitchFigure 3. High Speed RF Module with Die to Interposer Integration ¨C (down to 80μm), small bump sizes (down to 50μm), vision recognition of the2 RF Devices and 2 Processors to TSV Interposerchip and substrate during assembly, reflowing of the flip chips on a wafer, andunderfilling a bumped wafer with chip components in close proximity havebeen established. Initial reliability results are presented in references 8 and 9,which highlight that even though the flip chip is mounted silicon-to-silicon,the pitch and bump size make it so that the underfill selection has a largeimpact on the reliability of the assembly. Various aspects of the D2W assemblyprocess have been explored, including scaling issues with high-volumeassembly, utilization of low-cost underfill approaches such as no-flowunderfills, wafer-applied underfills, and underfill encroachment on the WLCSPballs. Finally, data on 2nd level reliability of the 3D WLCSP has beenestablished, indicating robust reliability of the 3D-WLCSP assemblies mountedon conventional printed circuit boards. 8,9Further density opportunities are emerging in the wafer-level 3D packagingspace as TSVs ramp in production. Figure 5 shows a 3D-WLCSP incorporatingTSVs in the base wafer (PA) and flip chip die (ACTs) mounted on the backside of the silicon. In this case, the base wafer requires thin-film wiring orredistribution interconnect on the top side of the wafer routed to capture theTSVs as well as the flip chip ACTs. Using this 3D-WLCSP architecture, theentire base die area can be utilized for ACT die bonding, the inter-dieinterconnect lengths can be minimized improving performance, and the ACTand PA die can be probe tested to minimize the yield loss.Figure 4. 3D Wafer Level CSP technology (a) Flip Chip Process Flow, (b)SummaryWafer Level Assembly and Singulated 3D-WLCSPs. (c) ACT Die Flip As the move to higher performance and smaller form factor electronicsChip Mounted to PA Wafer, (d) ACT to PA Flip Chip Interconnect continues, 3D die level integration has moved to the forefront as an22 Chip Scale Review May/June 2011 [ChipScaleReview.com]

Figure 5. Routing on multiple gridsapplication solution platform. Whilecurrent 3D packaging solutions involvinga combination of high density circuitboards with wirebonded stacked ICs cansatisfy some of the performance and formfactor requirements, 3D die levelintegration is proving to be the solutionof-choicefor many mission critical, highreliabilityapplications. The key featuresof the technology are very high levels ofintegration, very small form factorpackages often chip scale in size, very lowprofile packages, low weight packages,and improved digital and RF performance.This paper has revieweded 3D integrationtechnologies, presentedimplementation strategies for3D die level integration forchip size packaging, andpresented examples of 3D dielevel integrated packagingsolutions.References1. Garrou, P. “Posturing &Positioning in 3-D ICs,”Semiconductor International Magazine,April 1, 2007.2. Garrou, P. “Wafer-Level 3-D IntegrationMoving Forward,” SemiconductorInternational Magazine, October 1, 2006.3. Hopkins, J., et al. “Through-wafer ViaEtching,” Advanced Packaging, April,2005.4. T. G. Tessier, D. Scott, D. McComband R. Forcier, “Mobile Handsets DictateFlip Chip and Wafer Level PackagingTrends”, Semicon West, July 2008.5. “Chip-On-MEMS HeterogeneousIntegration of MEMS and Circuits”,www.vti.fi/en/products/technology/com/6. Stout, G. A., Tessier, T.G., Clark, D.Houston, P., Baldwin, D. F. Li, Z., “3D-WLCSP Package Technology:Technology and Design Considerations,”Proceedings of the International WaferLevel Packaging Conference, San Jose,CA, Oct. 13-16, 2008.7. Li, Z., Evans, J. L., Lee, S., Baldwin,D. F., Lewis, B. J., Houston, P. N., Stout,G. A., Tessier, T.G., “Sensitivity Analysisof Pb Free Reflow Profile ParametersToward Flip Chip on Silicon AssemblyYield, Reliability and IntermetallicCompound Characteristics,” Proceedingsof the Electronics ComponentsTechnology and ManufacturingConference, Las Vegas, NV, June 1-4,2010.8. Li, Z., Houston, P. N., Baldwin, D. F.,Stout, G. A., Tessier, T.G., Evans, J. L.“Design, Processing and ReliabilityCharacterizations of a 3D-WLCSPPackaged Component,” Proceedings ofthe Electronics Components Technologyand Manufacturing Conference, SanDiego, CA, May 26-29, 2009.Chip Scale Review May/June 2011 [ChipScaleReview.com] 23

Taking the Fear and Pain out of 3D MigrationBy Lisa McIlrath, [R 3 Logic, Inc.]3D Integration is touted as beingthe solution to the end of scaling,but the fact remains that there are stillmany hurdles to overcome in both thedesign and manufacturing arenas. Costis one of the major factors in the decisionto migrate to 3D technologies or not, andthe ability to leverage tried-and-true IPlibraries developed at different processnodes can represent a significant savingsin both design and manufacturing costs.3D EDA tools must allow designers torapidly assess the benefits of a particularstacked configuration including thepackage and possibly interposer layers,while maintaining existing 2D designflows and methodologies.Elements of FearThe only thing wrong with 3D integrationis that the supply chain is uncertain; wedon’t have good device models (thermal,mechanical, or electrical), and we don’tknow how to test the die in the stack.Otherwise, it’s really great.It takes a lot of pain to push a multihundredbillion dollar industry to changeits ways, and a lot of reward from anynew technology to keep it changed. 3DIntegration is exciting, but is it worth therisk to my business to chase afteruncertain benefits? What are the real costand/or performance gains that can beachieved? How can I quantify these andjustify the risk?In the 2D world, designers have thebenefit of well-studied models that can berelied upon to closely approximate systembehavior under a range of conditions. Thisfrees them to focus on design at theabstract, or system level. In 3D, suchmodels are incomplete or virtuallyinexistent as far as fabless companies areconcerned. Consequently, there is nochoice but to descend into the physicalimplementation of the stack to ensure thatperformance criteria can be met. To date,however, few design tools have beenavailable to permit true-3D analysis,spanning multiple die and multipletechnologies. Why not? What is so specialabout 3D that makes 2D tools inadequate?We want to answer these questions,define exactly what a true-3D tool is anddescribe what functions are needed to make3D design decisions with confidence.3D Design Tools to the RescueDesigning in three dimensions looks alot easier than it actually is. Most peoplewho have done it will attest to the fact thatone can design 3D systems by patchingcurrent 2D tools with scripts and varioushacks, but in the words of one veteran 3Ddesigner, it is like “repairing your car withchewing gum and scotch tape”.Given that the objective is to reducedesigner pain rather than to increase it,let’s briefly state the bare minimumrequirements of a true-3D EDA tool:● Use of independent technology filefor 3D rules and configuration● Ability to use existing 2D PDKs andstandard cell libraries without change● Ability to maintain the integrity of3D multi-tier cells while editing 2Dviews (and vice-versa)● Plug-and-play compatibility withexisting flowsThere are so many possibilities forconfiguring a 3D stack (with or withoutinterposer, face-to-face, face-to-back, etc.)and so many ways of combining differentdie technologies (Figure 1)that the need for 3Dtechnology independenceshould be self-evident. Itshould be equally obviousthat the designer should notchange any portions ofexisting 2D PDK’s orlibraries _ even if someonealready wrote automatedscripts to perform this task.A TSV is the simplestexample of a 3D cell(Figure 2), in whichdifferent components ofthe cell reside on differentdies. If one part of theTSV is moved or deleted, the rest of it mustbe moved or deleted as well.Plug-and-play compatibility is essentialbecause the fact is that existing tools canalready almost do the job. The role of thetrue-3D EDA tool is to gracefully fill thegaps not covered by current 2D tools. Todo this well and thoroughly, it must workwithin an open standards framework forpassing file information to and from theexisting toolset. For example, a 3Dfloorplanner should provide the partitionednetlists and pre-placed TSV positions foreach tier to a 2D place-and-route tool.After placement and routing of each tier,the 3D structure must then be recoverableso that electrical and design ruleverification can occur across the tiers. Inother words, the 3D connectivity andplacement information must survive thepassage through the 2D design flow, andany changes made to the individual tierdesigns that affect the 3D structure, forinstance moving part of a TSV cell, mustbe reflected back to the 3D database.Maximizing 3D PerformanceUntil there are a number of successful3D demonstrators and a body ofknowledge of 3D design best practices hasevolved, there will remain a great deal offear and reluctance to betting the farm onthis new technology. The afore-mentionedFigure 1. Stack topology and die technologies are specified in a distinct 3Dtechnology fileFigure 2. A TSV seen as a 3D cell24Chip Scale Review May/June 2011 [ChipScaleReview.com]

Figure 3. System partitioning alternativesbasic features of a true-3D tool are onlyjust that _ basic. To really showconvincingly that there is a true cost and/or performance benefit to 3D chipimplementation, a 3D pathfinding tool hasto be able to dive deep enough into thephysical design of the stack so that onecan have confidence that the performanceparameters it predicts are meaningful.In addition to the baseline features thatmust exist in any 3D EDA tool, we identifyfour essential capabilities needed for efficientdesign space exploration (aka pathfinding)to rapidly find the sweet spots for 3D.2010. These 2.5-D systems, asthey are often called, are vitalto establishing the supplychain for 3D manufacturing.The demand for interposerbasedstacks will provide theimpetus for developing robustTSV processes, which areneeded before widespread 3D fabricationand commercialization can occur.TSV planning and assignment is crucialin a 3D pathfinding tool because evenslight changes in functional blockplacement on one tier can lead tosignificant cost increases due to theirimpact on other tiers. Take for examplethe configuration shown in Figure 4. Theleft-hand image shows signal flight-linesfor a 2-die system flipped directly onto aBGA. The die are arranged diagonally to1. Ease of IP re-use and re-configurationIf nothing else, being able to useexisting, proven IP libraries for the majorityof the stack, as opposed to re-characterizingeverything in an SoC for a new technologynode, represents a huge cost savings in andof itself. It remains to show that there is aconcomitant performance or cost benefitexceeding that of going to the nexttechnology node. The only way to do thiswith any level of confidence is through trialplacement of the hard macro blocks calledfor in the architectural design, followed byroutability and signal integrity analysis.This implies that the designer must havefull flexibility to choose both the tierplacement and the IP library for eachblock, and that the 3D tool should partitionthe netlist accordingly (Figure 3).2. TSV planning and assignmentIn the early days of 3D adoption, one hasto expect that to minimize cost and risk,the initial 3D stack architectures _ at leastthose produced commercially _ will belittle more than stacked versions of 2Dsystems. This being said, there aresignificant cost savings and performanceimprovements that can be achieved byintroducing interposers with TSVs just tofacilitate routing and increase bandwidth.A prominent example is the Xilinx 4-Virtexon-interposersystem announced in OctoberChip Scale Review May/June 2011 [ChipScaleReview.com] 25

Figure 4. Impact of interposer on package designminimize cross-over, but still two metallayers are required to route the traces onthe package. Thelegitimate question isthen: “Can we dobetter with a 2.5D(3D) arrangement?” Isit possible to improvesignal delay betweenthe two die, not changethe package footprintor pinout _ because that impacts theentire product line _ and decrease thecost of the package by removing a routinglayer?Since the inteposer area is one costelement, we move the two die as closetogether as possible. Suddenly theflight-line crossover is much worse _now what? The 3D pathfinding tool hasto step in to find the solution by helpingto generate a TSV arrangement that canachieve the best compromise for routingboth the interposer and the package. Inthe case at hand (Figure 5) it wasFigure 5. TSV placement and assignment tominimize cost and maximize routabilitypossible to find a solution that reducedthe packaging cost (by removing arouting layer) and improved signalintegrity and bandwidth between thetwo die. Signal crossover was handledon the passive Si interposer where thecost of using three metal routing layerswas significantly less than using two onthe package.3. Multi-grid routingAn important point of the previousexample is that the package substrate wasmodeled in the 3D pathfinding tool as justanother tier _ a perfectly logicalconsequence of the fact that any 2Dtechnology, including that of the package,can be specified in the 3D technology file.The use of multiple disparate technologiesalso implies multiple disparate manufacturinggrids and hence, for true inter-tier co-designto take place, multiple routing strategies areneeded as well. Contrast for example thepackage-to-TSV routing in Figure 6 withthat of the interposer-to-TSV routing on theright-hand side of Figure 5.4. Signal / power integrity and IR dropanalysisBeing able to place and assign TSVs andperform trial routing is critical for 3Dpathfinding if the goal is to verify that 3D(continued on Page 48)26Chip Scale Review May/June 2011 [ChipScaleReview.com]

32Chip Scale Review May/June 2011 [ChipScaleReview.com]

"Electronic Consulting Network" (480) 215-2654 www.aztechdirect.com Submit all Directory inquiries and updates to surveys@aztechdirect.comINTERNATIONAL DIRECTORY OF WAFER BUMPING FOUNDRIESDirectory data was compiled from company inputs and/or website search and may not be current or all-inclusive as of the date of publication.COMPANYHEADQUARTERSBUMPTECHNOLOGIESPROCESSCAPABILITYBUMPCOMPOSITIONCompanyStreet AddressCity, State, CountryTelephoneWebsiteCM = Contact ManufacturerBumping MethodBall DropElectrolessElectro PlateSolder JetStencil PrintBasic SpecificationsBP - Bump Pitch (um)WD - Wafer Dia. (mm)UBM - Under Bump Metal(s)Electroless UBMSputtered UBMBump MetalAU - GoldCP - Copper PillarSEU - Solder, EutecticSHL - Solder, High PbSLF - Solder, Pb-FreeNEPES, Pte. Ltd.12 Ang Mo Kio Street 65Singapore 569060Tel: +65-6412-8181www.nepes.com.sgElectro PlateBP: > 50WD: 200, 300UBM: Ni, CuSputtered UBMCPSEU, SHL, SLFPac Tech GmbHAm Schlangenhorst 7-9 & 15-1714641 Nauen, GermanyTel: +49-3321-449-5100www.pactech.deBall DropSolder JetStencil PrintBP: > 80WD: 100, 150, 200, 300UBM: Ni+Au, Ni+PdElectroless UBMSEU, SHL, SLFOtherSemiconductor Mfg. International Corp. (SMIC)No. 18, Zhangjiang Road, Pudong New AreaShanghai 201203, P.R.C.Tel: +86-21-3861-0000www.smics.comCMBP: CMWD: 200, 300UBM: CMAUSEU, SLFSiliconware Precision Industries Co., Ltd.No. 123, Sec. 3, Da Fong Rd., Tan tzu,Taichung 427, Taiwan R.O.C.Tel: +886-4-2534-1525www.spil.com.twBall DropElectro PlateStencil PrintBP: > 100WD: 200, 300UBM: CMSputtered UBMCPSEU, SLFSTATS-ChipPAC Ltd.10 Ang Mo Kio Street 65, #05-17/20 Technopoint,Singapore 569059Tel: +65-6824-7777www.statschippac.comBall DropElectro PlateStencil PrintBP: 150 - 600WD: 150, 200, 300UBM: Ti/NiV/Cu, Ti/Cu/Cu/NiSputtered UBMCPSEU, SHL, SLFTLMI Corporation2111 W. Braker Lane, #500Austin, TX 78758Tel: +1-512-833-7075www.tlmicorp.comElectro PlateBP: > 20WD: 75 - 300UBM: Ti+Cu, Ti+WSputtered UBMAUCPSEU, SHL, SLFOtherTaiwan Semiconductor Mfg. Co., Ltd. (TSMC)No. 8, Li-Hsin Road VI, Hsinchu Science ParkHsinchu, Taiwan 300 R.O.C.Tel: +886-3-563-6688www.tsmc.comCMBP: > 140WD: 150, 200, 300UBM: CMCPSEU, SHL, SLFUnisem (M) Berhad9th Floor, UBN Tower, No. 10 Jalan P. Ramlee,50250 Kuala Lumpur, MalaysiaTel: +60-3-2072-3760www.unisemgroup.comBall DropElectro PlateStencil PrintBP: CMWD: 100, 150, 200UBM: CMAUCPSEU, CMChip Scale Review May/June 2011 [ChipScaleReview.com] 33

Industry INDUSTRY Happenings HAPPENINGSSEMICO Research Summit: An Executive Perspective on the New Frontier for SemiconductorsPainting a bright future for the electronicsindustry driven by smart technologies, avaried assortment of industry executivesfrom across the semiconductor supply chainoffered insight at the SEMICO ResearchSummit, May 1-3, 2011. The theme of thetwo day event was “The New Frontier,”which is being paved largely by theopportunities afforded by the recent waveof smart technology: phones, tablets,homes, etc. Taking advantage of theseopportunities will require a new approachpretty much across the supply chain.Offering a snapshot of SEMICO’sindustry analysis, Jim Feldhan, CEO, openedup the proceedings. He talked about globaleconomics, giving a country-by-countrybreakdown, stressing how we really need topay attention to the world environment. TheUS is gridlocked, causing deficit phobia,decimating educational investments, and theinfrastructure is being ignored while othercountries are investing heavily. He alsotouched on the aftermath of the earthquake/tsumani/nuclear disaster in Japan; noting thatwhile it will take Japan 3 years to rebuild,the world-wide effect will be short-lived. Hepredicted that electronics supply chainshortages will be over by September, andspot shortages will actually result in pent-updemand and stimulate growth in 2012. Onelesson learned is that there needs to be aglobal balance in the supply chain so thatsources aren’t limited to one geographicalregion, in case of natural disasters.Feldhan also set the stage for theremainder of the summit, calling theexplosion in smart phones the “PromisedSEMI-THERM 27 AttendanceUnderscores the Importance ofThermal ManagementThe 27th annual IEEE SemiconductorThermal Measurement, Modeling andManagement (SEMI-THERM) Symposiumwas held March 20-24, 2011, in San Jose,CA. This marked the first year thatMEPTEC co-located its annual one-daythermal packaging workshop with theLand” with lots of leading-edge chips forbaseband and applications and processorsand memory. And the market for MEMSand sensors is expected to grow 58% in 2011.Adapting to the speed and product driversof this New Frontier will, more than anything,require changes in the way things are done.As Danny Biran, Sr. V.P. of Marketing,noted, historical definitions are becomingmeaningless. With regard to the previouslyclearly defined purposes of ASICs, FBGAs,ASSPs, and μP/DSP, those lines are nowblurring. With improved processtechnologies and design techniques, morefunctions can be implemented on the samedie. With these converging platforms, Biransays that semiconductor companies mustcreate new types of products to succeed.“Rethink priorities, needs, your developmentorganization, and skill sets,” he advises. “Letthe product drive the structure of organizationand design methodologies. Engage withplatform vendors early on in the process _don’t make assumptions of what can or can’tbe done.” This way, he says you can ensureyou get the best combination of flexibility,time to market, performance, and cost.The importance of open communicationand collaboration going forward wasanother underlying sentiment voiced bymany of the speakers. Gregg Bartlett,SVP of Technology and R&D,GLOBALFOUNDRIES, said the mobileelectronics experience is enabled bysilicon innovation. At 20nm and beyond,he says packaging integration is no longeran afterthought, but rather a dominatingcontributor to the value chain because itSEMI-THERM event.The 5-day event showed increases inattendance and course offerings acrossthe board over 2010. It attracted 198offers opportunities to lower cost andaccelerate time to volume. 2.5D and 3Dprocesses give system level designers anotherknob to allow for repartitioning products.Bartlett says that this calls for a collaborativeenvironment, where foundries work togetherwith OSATS to jointly develop IP solutionsfor customers. He proposed a new globalmodel for collaboration calling for advancedresearch and early engagement across thecustomer base. Likewise, involving theEDA and packaging communities early onis vital. It’s important to establish design rulesthat can be substantiated in technology, andto foster a multi-sourced, geographicallydispersed supply chain. Aart De Geus,founder of Synopsys, concurred, saying thatfor future technology generations, softwaredevelopment needs to take place along withhardware development, rather than waitingfor the hardware to be ready to go beforedeveloping software.Perhaps Moshe Gavrielov, President &CEO, Xilinx, Inc. voiced best what isneeded when he quoted Charles Darwinis saying “It’s not the strongest of thespecies or smartest that survive, but theone most accepting of change.” Inaddressing skepticism about makingprogress in semiconductors below 30nm,Joe Sawicki VP and GM, Design-to-Silicon, Division Mentor Graphicssuccinctly summed up what applies forall moving forward. “The only onerational approach to looking forward iswith WILLFUL OPTIMISM, and continueto deliver on what is possible; even if it’sthought to be unachievable.”symposium attendees (up 43%) to 44short courses (up 83%) and 486 totalregistered attendees (up 66% over 2010).There were 38 exhibitors (up 31% over2010), reported Tom Tarter, Exhibitor andConference Manager, and President ofPackage Science Services, LLC.“SEMI-THERM 27 demonstrated,through increased symposium andexhibition attendance, that the electronicsindustry is recovering from the downturnover the last several years and that the34Chip Scale Review May/June 2011 [ChipScaleReview.com]

thermal management aspects of theindustry remain of high importance. Therecovery also led to a significant increasein the number of exhibitors, maintainingSEMI-THERM as the premier venue fordisplaying and introducing new electronicsthermal management products andservices.” noted Bernie Siegal, Presidentof Thermal Engineering Associates, Inc,and Steering Committee Operations Chair,Keynote speaker, William Chen ofASE Group, kicked-off the event with aprovocative presentation titled, “Engineeringthe Packaging Revolution.” Jim Wilson ofRaytheon was honored with theprestigious 2011 THERMI Award for hiscontributions to the field, and DirkSchweitzer of Infineon Technologies AGreceived the Harvey Rosten Award forExcellence for his paper.“The conference had an impressiveturnout of attendees from various parts ofthe world e.g. North America, Asia (HongKong, Taiwan, China, Japan, Korea, andIndia) and Europe (Russia, Poland,Germany, Turkey, Belgium, Hungary, andthe Netherlands).” remarked General Chair,Sai Ankireddi, PhD., Sr. Principal Engineerat Intersil Corp., “The participation by theseengineers, technologists and scientists fromall over at this annual symposium istestament to SEMI-THERM’s trulyinternational stature, and to its position asthe de-facto forum for practical knowledgeand experience sharing in the areas ofthermal measurement, management andmodeling.”SEMICON West 3D and AdvancedPackaging Program: Having Cakeand Eating It TooThis year’s 3D integration andAdvanced Packaging Programs atSEMICON West, July 12-14, 2011, inSan Francisco, CA, are shaping up to bereal crowd pleasers. The SEMI AdvancedPackaging Committee, chaired by BillChen, ASE Fellow, has been hard at workmaking sure all bases are covered in thisexpanding market sector from 3Dintegration, heterogeneous integration ofMEMS and sensors to the latest in‘contemporary’ packaging and waferlevelpackaging (WLP) processes. In fact,so much ground to cover called for theexpansion of the original time slots.Divided on three different stages overtwo days, this year’s programs will followa keynote/panel discussion format withrepresentatives from across the supplychain assembled to discuss challengesand solutions for each focus area.Heterogeneous Integration withMEMs & SensorsWith double-digit growth forecast forthe MEMS industry, more MEMS devicesand sensors are finding applications in theglobal market place. Smart phones,handheld gaming devices and consoles,and automotive applications are leadingthe charge. With devices on the marketranging from pressure sensors, RF-MEMs,accelerometers and gyroscopes, tomicrophones, micro-actuators, compasses,CMOS image sensors, chemical sensors,microfluidics, and mirrors and displays,there’s no doubt that MEMS are growingfast. To paraphrase ITRS, the intersectionof Market and Technology is calling for“More MEMS and More Than MEMs”.This session will focus on key players inthe system, device manufacturer, OSATand consortia segments of MEMS.Chaired by Klaus-Dieter Lang, Fraunhofer- IZM Director, keynote speeches for thissession will be delivered by an industryvisionary (TBD) and market analyst,Jan Vardaman, president, TechSearchInternational. At press time, confirmedpanelists include M. Juergen Wolf,Fraunhofer IZM, Yoshiaki Sugizaki,Toshiba Corp, and Gilles Poupon, CEA-Leti, They will be joined by several otherChip Scale Review May/June 2011 [ChipScaleReview.com] 35

36Chip Scale Review May/June 2011 [ChipScaleReview.com]

epresentatives from across the MEMSand packaging ecosystem from academiathrough the supply chain.3D in the Deep Submicron Era3D is about much more than 3D-IC andMoore’s Law Scaling. The drive for 3DIChas spawned a whole ecosystem for TSVtechnologies ranging from industry,academia, and research institutes toequipment and materials suppliers.Silicon interposers based upon TSV _thus inspiring the term 2.5D _ havebecome critical in the first wave of 3Dimplementation. From high-performancenetwork systems and servers to laptops,tablets, mobile systems and gameconsoles, the silicon interposer representsa solid fork in the highway for 3Dimplementation, thus raising thequestions: What is the silicon interposerecosystem? Is the industry infrastructurein place for high-volume cost-efficient 3Dimplementation? What will the next stepbe? In the world of “More Moore andMore Than Moore”, 3D silicon interposertechnology enables the industry “to haveits cake and eat it too”.Session chairs Jie Xue, Cisco, and GamalRefai-Ahmed, AMD, are organizing agroup of experts on these topics to addressthese specific questions and concerns.Divided into two sub-sessions, the first willaddress 2.5D integration using siliconinterposer technology, and will kick off witha keynote address from industry visionary,Vincent Tong, Senior VP at Xilinx. followedby a panel discussion moderated by SitaramArkalgud, 3D IC program director atSEMATECH. Confirmed panelists includeRao Tummala, of Georgia Tech’s 3DPackaging Center; Ron Huemoeller, SeniorVP, Advanded 3D interconnects, Amkor;Jon Greenwood, Senior Member ofTechnical Staff, Technology & IntegrationGLOBALFOUNDRIES, and others.The second session will feature akeynote by well-known market andtechnology analyst, Jean-Marc Yannou,of Yole Développement. The ensuingpanel discussion, 3D PackagingTechnology and Ecosystem, will examinethe state of the 3D market and itsremaining hurdles. Confirmed panelistsnow include Bill Bottoms Chairman andCEO Third Millennium Test Solutions,Inc. (3MTS); Rozalia Beica GlobalDirector of 3D Interconnect TechnologyTransfer and Integration of AppliedMaterials; and Calvin Cheung VP ofEngineering, ASE U.S.Contemporary Package Challengesand Solutions for 40nm and BeyondMuch has been written about emergingtechnologies for the 40nm fab node (andbeyond), such as CU pillar FC, ELKcompatibility and 3D TSV. However,product-level applications for thesetechnologies tend to focus onperformance-driven market segments;markets that are better-able to fundtechnology development and can accepthigher initial risk. But what about marketsegments that account for up to 70% ofour industry and are driven largely bylow-cost and low-risk? Are cost-effectiveIC package solutions available for marketsegments such as handheld, consumer andautomotive as they migrate to smaller siliconlithographies in search of cost reduction?When faced with the decision to use anadvanced fab node, will these companies:● Change package interconnecttechnology?● Change package and PCB technologies?● Change system architecture?● Adopt new technologies such as FO-WLP and TSV?● Continue to use the existing fab node● Do something else?Co-Chaired by Tom Gregorich ofMediaTek and Rich Rice of ASE, oneof two keynotes will be delivered byJim Walker, Research V.P. Panelistsinclude Doug Yu, Sr. Director ofInterconnect and Packaging, TSMC;Andreas Knoblauch, Director PackageDevelopment Automotive, InfineonTechnologies; Mike Ma,V.P, R&D,Siliconware Precision Industries Co.,Ltd (SPIL); and Fernando Chen, SeniorDirector, Laminate Products & TechnologyMarketing, STATS ChipPAC.(continued on Page 44)Chip Scale Review May/June 2011 [ChipScaleReview.com] 37

WHAT'S NEW!Molded Flip Chip Imaging EnhancementMolded Flip Chip Imaging (MFCI)enhancement from Sonix was designedto improve image quality and defectdetection in molded flip chips andpackages with polyimide (PI) layers byreducing the impact of the scatteringand attenuation effects of filler particlesin mold compounds and PI layers. Fillerparticles increase scattering ofultrasonic signals, causing shadows inthe images, and in some casescompletely obscure solder bumps andCu pillars, resulting in reduced imagequality and inaccurate defect detection.Also, the polyimide materials (PI) usedto improve the thermal properties ofthinner dielectric layers attenuate theultrasonic signal, further degradingimage quality and defect detection.Configured through Sonix WinIC TM ,Sonix MFCI improves the spatialresolution, contrast and edge definitionwhen inspecting samples containingmaterials that scatter or attenuateultrasonic signals. Sonix MFCI isavailable as an option on all Echo TM ,Echo Pro TM and AutoWafer TM tools, andas a field upgrade on all Sonix Fusion TMand Vision TM tools. [sonix.com]Triple Stacked Spring Pin SocketIronwood Electronics’ triple stackedBGA socket (CBT-BGA-7007) addresseshigh performance requirements for testingprocessor and memory simultaneouslyalong with a memory proe.-. Two differentspring pin technologies were utilized in thedesign _ 0.5mm pitch stamped spring pins,which have 26 gram actuation force perball and cycle life of 500,000 insertions;and 0.4mm pitch etched spring pins, whichhave 4 gram actuation force per ball andcycle life of 500,000 insertions. Thestamped spring pins are used in betweenmemory and memory probe as well asbetween memory probe and processor top.The etched spring pins are used in betweenprocessor bottom and target PCB. Sockettemperature range is -55C to +180C. Thesocket also features a floating guide forprecise ball to pin alignment.The CBT-BGA-7007 was designedspecifically for testing processor BGA,12x12mm, 0.4mm pitch, 520 position,29x29 ball array in the bottom socketand a memory BGA, 12x12mm, 0.5mmpitch, 168 position, 23x23 ball array inthe top socket. The socket is mountedusing supplied hardware on the targetPCB with no soldering, and uses thesmallest footprint in the industry,allowing inductors, resistors anddecoupling capacitors to be placed veryclose to the device for impedancetuning. [ironwood.com]Reballing Preforms for Wafer LevelPackageEZReball TM from BEST Inc. are saidto be the finest pitch, smallest balldiameter reballing preforms worldwide.Now available in ball sizes down to 8mils (0.20mm), these preformsaccommodatedevices downto 0.4mmpitch sizes.Solder spherealloys areavailable inlead-free, tinleadand high temperature alloys. Theperforms are suited to leading-edgeusers who need to reball wafer-levelcomponents down to 0.4 and 0.5pitches. Additionally, they can be usedto help diagnose and troubleshootcomponent problems. EZReball TMpreforms are available in packages of(15) preforms and come with a QCstencil in the package. [www.solder.net]Advanced Macro Inpection ModuleThe F30 TM Advanced MacroInspection Module, introduced byRudolph Technologies, is said to furtherextend the capabilities of the Explorer®Inspection Cluster product line.Foundries and IDMs that have installedthe module report improved throughputover the entire sensitivity range whencompared to previous generation tools.The hardware platform is capable ofsupporting 450mm development, and isdesigned to accommodate futurecustomer requirements and capabilities.The F30 Module features a flexibleblend of throughput and detectionsensitivity, resulting in a lower CoO. Itcombines automated setup, intelligentsoftware and robust capabiltity stagedon staged on a flexible platformdesigned to accommodate additionalcapability as defined by customerrequirements. [rudolphtech.cm]Reworkable Edgebond AdhesiveZymet Inc.’s UA-2605 is areworkable edgebond adhesive that issaid to improve thermal cycleperformance of CBGAs and plasticBGAs. According to the company, inone trial, UA-2605 tripled the 0 o C to+100 o C performance of a CBGA, tonearly 2500 cycles. Previously, anunderfill was needed to achieve thislevel of performance.This edgebond adhesive is reportedlyeasier to process than an underfill. WithUA-2605, only one bead of adhesive ateach corner is required. There is noneed to preheat the board, wait forunderfill flow, or multiple dispensingpasses. Additionally, BGA rework is38Chip Scale Review May/June 2011 [ChipScaleReview.com]

simple and straightforward. Thetemperature is raised and the adhesiveis scraped away; then, the BGA isreflowed and lifted from the board.[zymet.com]High Resolution 3D X-ray MicroscopeThe VersaXRM-500 from Xradia is a3D X-ray microscope featuring aversatile combination of reportedlyworld-leading resolution and contrast,sample flexibility, and the largeworking distance required to addressemerging research challenges in manymarket segments including thesemiconductor industry.The VersaXRM family builds on theresolution, contrast and versatilityinherent in Xradia platforms, includingtrue submicron spatial resolution, evenwhen positioned only millimeters fromthe source. The system featuresflexibility for correlative microscopywith multi-length scale imaging usingthe VersaXRM in conjunction with theUltraXRM or other microscopytechniques. The combination of betterworking distance and imagingflexibility extends the value ofmicroCT, improves throughput.Additionally, it offers the only nondestructivesubmicron resolutiontomographic capability, able tovisualize buried features without depackaging,cutting, or otherwisedestroying the device, a process thatcan potentially introduce physicalartifacts. This can also prevent the lossof critical information about the rootcause of the failure as a result ofdestructive imaging methods.“The package assembly roadmap callsfor an increasing number of stacked diceand interfaces, substantial developmentsin 3D interconnections, new materialcomposition, and increasing componentdensity while reducing criticaldimensions,” says Mario Pacheco, StaffR&D Engineer at Intel. “These trendsand developments translate intochallenges for defect isolation andcharacterization that are outpacingtraditional failure analysis techniques.Xradia’s developments in throughputand resolution address crucial gaps infailure analysis with a faster, nondestructivetechnique enabling highresolution characterization of intactpackages.” [Xradia.com]Conductive Die Attach FilmWith the introduction of a novelmaterial formulation, Ablestik C100series conductive die attach films fromHenkel enable leadframe packagemanufacturers to realize the advantagesof film-based solutions formerly onlyavailable for non-conductive processes.Established benefits over traditionalpaste die attach reportedly include theelimination of die tilt, ability to processthinner die, and greater bondline control.These die attach materials are said toprovide a high degree of manufacturinglatitude. Workability has beenestablished on die sizes ranging from1mm x 1mm up to 6mm x 6mm for avariety of package types including bothQFNs and QFPs. Additionally, thematerials’ better wetting ability withlower bonding temperature providesstable adhesion strength for robustadhesion against moisture and MSLLevel 2 performance on all leadframesurface finishes. [Henkel.com/electronics]Chip Scale Review May/June 2011 [ChipScaleReview.com] 39

(continued from Page 29)show strong grain contrast in manymetallic samples due to “ion channeling”contrast in the secondary electron image.This makes the ion beam an excellenttool for not only sectioning, but alsoimaging such interconnect and IMCsamples.In a second paper at IMAPS, theplasma-FIB was also applied to aninvestigation of W2W bonding using ananisotropic conductive adhesive. 8 Thisbonding was achieved using metal-coatedpolymer spheres (4μm in diameter) in abenzocyclobutene polymer matrix. Figure4 shows a section through the interfaceregion where the interconnecting spheres4(a)4(b)Figure 4. Plasma-FIB section and image throughW2W bonded interface. 4b shows a detailed viewof the bond, including two of the interconnectingspheres. Sample and images courtesy of SINTEFhave been precisely sectioned. The authorsreported a good correlation between thecontact area size and resistance, indicatinga satisfactory insulation between bondedareas, and noted that “a well controlledstand-off height was observed in FIBinspection of diced cross-sections.”Conclusion3D packaging integration continues toincrease in complexity, which is drivingmore samples into FA labs fordevelopment support, reliability studies,and failure analysis. FIB and dualbeamFIB/SEM provide key capabilities tosupport these activities, notably the abilityto provide site-specific sectioning andanalysis. In addition to the increase insample numbers, there is also a need forlarger removal volumes for many of thejobs, compounding the increased need fortool time and resources to meet thedemand. To address this, a number ofsystem and technology developments areimproving the throughput of the FIBtechnique; these include enhancements via40Chip Scale Review May/June 2011 [ChipScaleReview.com]

FIB-induced beam chemistry and the useof higher current ion sources, notably therecent introduction of FIBs based on theinductively coupled plasma ion source.Acknowledgements● Corey Senowitz, Sean Kellogg, ChadRue, and German Franz are gratefullyacknowledged for images shown, aswell as SEMATECH, FraunhoferEMFT, and SINTEF for samples.● A part of the work has been performedin the project JEMSiP_3D, which isfunded by the Public Authorities inFrance, Germany, Hungary, TheNetherlands, Norway and Sweden, aswell as by the ENIAC Joint Undertaking.References[1] For an overview on FIB techniquessee, for example, Introduction to FocusedIon Beams: Instrumentation, Theory,Techniques, and Practice, eds. L.A.Giannuzzi and F.A. Stevie, Springer, NewYork, 2005.[2] W.H. Teh, C. Deeb, J. Burggraf, M.Wimplinger, T. Matthias, R. Young, C.Senowitz, and A. Buxbaum: “RecentAdvances in Submicron Alignment 300mmCopper-Copper ThermocompressiveFace-to-Face W2W Bonding andIntegrated Infrared, High-Speed FIBMetrology”, Proceedings of 13th IEEEInternational Interconnect TechnologyConference, 2010.[3] P. Gounet, M. Mercier, D. Serre, andC. Rue,: “Failure Analysis of Through-Silicon-Vias Aided by High-Speed FIBSilicon Removal”, Proceedings of 16thIPFA, Suzhou, China, 2009, pp. 94-99.[4] N.S. Smith, W.P. Skoczylas, S.M.Kellogg, D.E. Kinion, P.P. Tesch, O.Sutherland, A. Aanesland, and R.W.Boswell: “High Brightness InductivelyCoupled Plasma Source for High CurrentFocused Ion Beam Applications”, J. Vac.Sci. Technol., 2006, B24 (6), pp. 2902-2906[5] S. M. Kellogg, A. Graupera, R.Hoelle, T. Miller, S. Zhang, D. Laur, andA. Dirriwachter: “A System for Massive,Rapid Material Removal for DeviceAnalysis in Monolithic 3D IntegratedCircuits”, Presented at 53rd InternationalConference on Electron, Ion and PhotonBeam Technology and Nanofabrication,Florida, May 2009[6] S.M. Kellogg, R. Schampers, S.Y.Zhang, A.A. Graupera, T. Miller, W.D. Laur,and A.B. Dirriwachter, “High ThroughputSample Preparation and Analysis using anInductively Coupled Plasma (ICP) FocusedIon Beam Source”, Microsc. Microanal.,2010, 16 (Suppl 2), pp. 222-223.[7] P. Ramm, A. Klumpp, G. Franz, andL. Kwakman: “Failure Analysis andReliability of 3D Integrated Systems”,Proc. IMAPS Device Packaging Conf.,Scottsdale, Arizona, 2011[8] M.M.V. Taklo, T. Bakke, H.R.Tofteberg, L.G.W. Tvedt and H.Kristiansen: “Anisotropic ConductiveAdhesive for W2W Bonding”, Proc.IMAPS Device Packaging Conf.,Scottsdale, Arizona, 2011Chip Scale Review May/June 2011 [ChipScaleReview.com] 41

Full Speed-Ahead for Flip ChipsBy Jean-Marc Yannou, [Yole Développement]Jean-Marc Yannou is in charge of advanced packaginganalysis at Yole Développement, including wafer-levelpackaging and 3D system integration. His 15 years of experiencein the semiconductor industry include serving asinnovation manager for system-in-package (SiP) technologiesat Philips/NXP Semiconductors, and years at TexasInstruments.The worldwide flip chip marketreached $16B in 2010, and isnow poised for extremegrowth as the technology continues toevolve and loses its reputation as a costlypackaging solution (Figure 1). AlthoughFigure 1. 2010 Total Flip Chip Market Value split by cost-of-ownershipsupply chain segments (substrates for LCD drivers excluded, servicemargin included) Total = $16Bthe flip chip market is large and wellestablished, it isn’t considered mature yet.In 2010, it accounted for 29% of the totalIC packaging market _ involving morethan 17B flip chip ICs.A serious growth phase is currentlyunderway, with an expected compoundannual growth rate (CAGR) for waferbumping in flip chip in package at 10.5%during 2010 to 2016, which is 2 pointshigher than the CAGR forecasted for theaverage semiconductor industry. 2011will be the first year to exceed 10Mbumped wafer starts for flip chip, and fabutilization is also greater than 95%.Why flip chip, Why now?Flip chip technology isn’t new. But itsrecent evolution toward copper pillarbumping is rapidly being adopted forconsumer, telecom, and industrialapplications as a leading alternative tosolder in the rush to meet RoHS lead-freeinterconnect requirements by 2014. Moreimportantly, while it was previouslydriven mainly by performance (and by theI/O interconnect gap resulting from therelentless Moore’s law), it’s now increasinglybeing driven by costconcerns. Additionally, newunderfilling technologiesand materials are enablinglower-cost flip chipassembly flows with goodreliability.Historically, flip chiptechnology has beenconsidered excessivelycostly. As such, the maindriver for adopting flip chip technologyhas never been low cost; it’s always beenelectrical and thermal performance forhigh-speed processors or for RF poweramplifiers. It’s also performance driven_ a different sort of performance _because it’s about light efficiency forhigh-power LEDS; and for CMOS imagesensors and SAW filters, it’s size orhermeticity, respectively.We may actually see flip chip pricesdrop significantly as volumes keep onincreasing. Flip chip costs are expectedto decrease slowly and progressively, butit is already very competitive with anumber of packaging platforms that usewire bonding. It’s important to note herethat the increasing price of gold isn’t oneof the primary factors behind the demandfor flip chip, because copper wirebonding is now widely used across allapplications.Copper pillar bumpsA significant evolution in flip chiptechnology, the copper pillar bump’s fastgrowth is quite surprising; as is the factthat a new technology could help withlowering costs in the packaging domainvery quickly, and at an industrial scale.This is fairly rare in the packaging domain.Typically, new technologies equate tohigher cost. In this case, it appears that itwill actually help decrease costs.One of the key reasons the copper pillarbump is so wildly successful is that it allowsfor much finer pitches and, at the same time,offers superior reliability and costs less.Finer pitches are possible becausecopper can be plated with aspect ratioshigher than 1, whereas the alternativesolder tends to collapse after reflow. Toachieve good reliability, a minimumbump height is necessary. Copper pillarbumps can be fine-pitch and high at thesame time. The height, which is the spacebetween the substrate and the IC, helpswith ease of flow of the underfill. Thismeans faster flow underfill techniquesand lower cost, thanks to copper pillars.In particular, “molded underfill” or“MUF” goes hand in hand with copperpillars and offers significant assemblyflow simplifications. Finer pitches alsodecrease the complexity of routing thesubstrates by enabling peripheralbumping and “bump on leads” (Figure2). So down the road we’ll need fewerFigure 2. A Copper column bump “Bonded on Lead”(Courtesy of StatsChipPac)42Chip Scale Review May/June 2011 [ChipScaleReview.com]

Figure 3. Intel’s copper pillar bumped packagessubstrate layers, which will also decrease cost. This is incrediblysignificant when you consider that more than 50% of the cost ofa flip chip package is its substrate.Intel began producing copper pillars in 2007 (Figure 3), whilethe next announcement to come from another company aboutadopting copper pillars wasn’t until 2010 when Texas Instrumentsand Amkor unveiled a partnership. Others, however, have beenusing copper pillars more discreetly, to package RF poweramplifiers or high side switches.We expect copper pillars to account for nearly 50% of the flipchip wafer bumping count in 2016 _ with the total more thandouble than that of solder bumping wafer count. The overall flipchip market has a CAGR of 8%. This may seem low, but it’sbecause some applications grow fast while others remain flat.Our forecast for copper pillar bumping for 2010 to 2016 is at aCAGR of 20%. When you think that flip chip (and semiconductor)world leader, Intel, switched to copper pillar bumps years ago, a20% compound annual growth rate is quite impressive. Copperpillar bumping will overtake the #1 position in bumpingtechnologies by 2013. Currently, gold-plated bumps for LCDdriver ICs are #1, but are expected to remain flat in the comingyears.Supply chain restructuring underwayTSMC is making massive investments in wafer bumping for flipchip and is now in position to vie with outsourced semiconductorassembly and test (OSAT) providers to provide this service. HowFigure 4. Cross section picture of Copper pillar bumps, (Courtesy of AmkorTechnology)might OSATs react? A smart way to retaliate is to focus on R&D _because no packaging R&D is done without the OSATs. They leadmost materials and process flow innovations. And right now, Amkor(Figure 4) and STATSChipPAC are getting lots of publicity abouttheir copper pillar bumping, which is something TSMC doesn’t haveyet. Concurrently, a new business model _ that of the “wafer bumpinghouses” specializing in wafer bumping services _ has emerged as asignificant player type in this market. All of this equates to somerather serious changes going on in the supply chain at the moment.Chip Scale Review May/June 2011 [ChipScaleReview.com] 43

But, during the next 3 years, we’re likelyto see foundries gain the upper hand withwafer bumping. The OSATs, however, willmore than likely maintain their strongpositions in both wafer bumping andassembly. Their business model enablesthem to control the supply chain well,because they provide the complete set offlip chip services, including package designand qualification, wafer bumping, substratein-sourcing, assembly, and final test.So it would be exaggerating to say thatvalue flows from the traditional back-endplayers to the front-end foundries. To someextent, this is true, but in the end, it seemsthat everyone has something to earn fromthis market growth, except maybe for thesubstrate manufacturers, who will need toinvest into new technologies like lowerCTE or thinner substrates while being ableto keep track of customers’ requested costdownroadmaps.By largely contributing to the consolidationof the “mid-end” wafer-level packaginginfrastructure, flip chip favors the fastgrowth of 3D wafer-level packaging withTSVs (they require similar infrastructures)and will benefit from it through the fastgrowth of silicon to silicon microbumping,and emergence of silicon and glassinterposers in flip chip packages. This isanother serious threat to high end ICsubstrate manufacturers: silicon and glassinterposers are a direct threat, and as ICsgo 3D, substrate-consuming technologiessuch as package-on-package will be phasedout. Fast-growing substrateless fan-outwafer-level packaging technologies (suchas Infineon/Intel’s eWLB) are fueling thisparadigm shift.Extreme growth aheadFlip chips are everywhere. They can befound in virtually every hot portablehandheld device and gadget, applicationprocessors, transceiver ICs, poweramplifiers, power management units,CMOS image sensors, telecom infrastructureapplications, automotive headlights andgeneral lighting appliances.The flip chip market essentially startedfrom scratch about 15 years ago and hasreached a remarkable $16B in that time.As the technology evolves, matures, andits cost decreases, flip chip growth shouldonly continue to soar.44(continued from Page 37)Chip Scale Review May/June 2011 [ChipScaleReview.com]Editor’s Note: This agenda is subjectto change, and more speakers will beannounced as they are confirmed. Staytuned for program updates on 3D InCites(www.3dincites.com) and in the July issueof CSR Tech Monthly. Details can alsobe found at www.semiconwest.org.Sneak preview of MEMS programs atSEMICON WestThis year’s main MEMS program atSEMICON West gathers some sectorleaders on Tuesday morning, July 12, todiscuss the future of the industry as moreof its output moves from a niche businessinto high volume markets. Speakersinclude:● Rakesh Kumar, Director, MEMS,Global Foundries, will talk aboutabout applying learnings from theCMOS industry to MEMS foundryproduction.● Jean-Christophe Eloy, CEO,YoleDéveloppement, presents the MEMStechnology roadmap, and how newprocesses and industrial infrastructurewill enable new applications.● Claude Jean, EVP and GM, Foundry,Teledyne Dalsa, will addressspecialty foundry issues and newtechnologies.● Jo De Boeck, SVP Smart systems &Energy Technology, IMEC, will reporton MEMS platform opportunitiesand SiGe options.● Gary O’Brien, Director AdvancedMEMS Design, Robert Bosch, willdiscuss new developments comingout of the labs.● Matt Crowley, VP CorporateDevelopment and Founder, Sand9,will update attendees on developmentsin packaging technology andoscillators for wireless.2011 IWLPC Sponsor UpdateSponsorships continue to roll in forthis year’s 2011International WaferLevel PackagingConference. TheSMTA and ChipScale Review arepleased to announce an additionalPlatinum Sponsor, NEXX Systems; aswell as several Gold Sponsors includingNANIUM,Europe’s largest outsourcesemiconductor assembly and test service(OSAT) provider; STATS ChipPAC, one ofthe top 5 OSATS worldwide, and packagingequipment manufacturer, Pac Tech.Platinum SponsorNEXX Systems, Inc. manufacturessemiconductor equipment designed expresslyfor wafer level packaging processing(WLP), addressingthe demandingeconomic andprocess flexibilityrequirements of the semiconductorpackaging industry. The Company has twoproduct lines: Stratus, an electrodepositionsystem offering breakthrough technologythat combines the process advantages ofvertical wafer orientation with the economicadvantages of parallel processing; andApollo and Nimbus, sputter depositionsystems designed to provide highthroughput and productivity, with lowconsumables cost.Gold SponsorsNANIUM provides design, development,engineering, and small to high volumemanufacturingservices forsemiconductorpackaging, assembly and test, operatingnamely in WLP and in traditional substrateand leadframe based packages. NANIUMwas one of the first companies worldwideoffering high volume manufacturing forfan-out WLP on 12” wafer, based onInfineon Technologies’ eWLB technology.The company is continuously developingnew solutions, like System-in-Package(SiP) at the wafer level, to stay at theleading edge of this technology. Thanksto 15 years’ experience in the semiconductorbusiness (as former Siemens Semiconductors,Infineon Technologies, and most recentlyQimonda Portugal), NANIUM has ahighly qualified and competent team andstate-of-the-art equipment and facilities,ready to provide services beyond its

clients’ expectations.STATS ChipPAC Ltd. is a leading service provider of semiconductorpackaging design, bump, probe, assembly, test and distributionsolutions. The company has the scale toprovide a comprehensive range ofsemiconductor packaging and test solutionsto a diversified global customer base servicing the computing,communications and consumer markets.Pac Tech Packaging Technologies is a worldwide leader in WLPservices and equipment. Pac Tech has over 15 years of experience inthe industry and has manufacturingsites all around the world, including:Germany, United States, Japan, andMalaysia. These sites can supply both engineering and prototypingservices, as well as high volume production. Pac Tech is structured toprovide a single source for all contract bumping services, as well asproviding turn-key WLP Equipment.There are still 2 silver level sponsorships available, as well ascoffee break, reception, lunch, and WiFi sponsorships. Contact KimNewman at knewman@chipscalereview.com.2011 IWLPC Program Takes ShapeThe technical committee has been hard at work recruitingkeynote speakers and organizing panels to make certain the 2011International Wafer Level Packaging Conference (IWLPC),October 3-6, 2011 is the best it’s ever been. Confirmed keynotespeakers include Matt Nowak of Qualcomm and Bill Bottoms, of3rd Millennium Test Solutions Additionally, each conference day(Oct. 5 and 6) will feature a panel discussion, one titled The Effectof Infrastructure on Technology Adoption, and the other Will 2.5Dand 3D Compete or Coexist?The four day event begins with two full days of Process andSix Sigma Certification workshops. Exhibits and tech sessionscomprise the remainder of the two conference days, offeringfull technology tracks on 3D, Wafer Level Packaging, andMEMS and many exhibitors showcasing their products andservices that support these market sectors.3D Panel Will 2.5D and 3D Compete or Coexist?The introduction of 2.5D silicon interposer solutions to meetthe performance, size and cost requirements of next generationconsumer electronics has the industry questioning whether thisis an interim solution while ‘true’ 3D addresses remaininglimitations of thermal, supply chain infrastructure and cost oftest issues; a complementary solution for 3D systems, or analternative avenue to 3D TSV altogether? In other words, will2.5D and 3D compete or coexist? This panel will discuss themotivations of these scenarios from the perspective of their corecompetencies. Confirmed 3D panelists include Ron HoemuellerSr. Vice President of Adv 3DIC, Scott Jewler, Chief Engineering,Sales and Marketing Officer at Powertech Technology; and PhilMarcoux, of PPM Associates, consultant for TSV technologies.Additional panelists will include experts in thermal management,Chip Scale Review May/June 2011 [ChipScaleReview.com] 45

46Chip Scale Review May/June 2011 [ChipScaleReview.com]

design, test, and an end user, and willbe announced as their participation isconfirmed.WLP Panel: The Effect of Infrastructureon Technology AdoptionThe adoption of any new semiconductortechnology depends heavily on the stateof the existing technology infrastructure.The IC-packaging industry is no exception.Established relationships and physicalstructures represent challenging obstacles,and enabling advantages, for newsemiconductor technologies. This panelwill discuss and evaluate the existingindustry infrastructure and thetechnological momentum driving, andregulating, adoption. It will also discussthe role of infrastructure in determiningtechnological progress. Panelists willinclude packaging experts drawn from topanalyst firms, key trade media and leadingindustry innovators, and will be announcedas participation is confirmed.MEPTEC/SMTA Medical ElectronicsSymposium Call for PapersSMTA and MEPTEC will once againbe joining forces to present the MedicalElectronics Symposium, September 27-28, 2011. The two-day technical programtitled “Medical Electronics-VitalTechnologies for Health” will be heldSeptember 27-28, 2011 at Arizona StateUniversity in Tempe, AZ. ASU’s Schoolof Biological and Health SystemsEngineering will co-sponsor this event.This symposium will focus on medicalelectronics and medical deviceapplications. The technical committee issoliciting abstracts from within themedical community that will share themost up to date information aboutcompany electronics expertise, practices,technology and applications as it relatesto the symposium topics. Deadline forabstracts is June 1, 2011.Session topics include:● Market Trends & Forecasts inMedical Electronics● MEMS Technologies for the MedicalIndustry● Manufacturing Technologies andStandards● Latest Developments in ImplantableProducts and Applications● System Level Products and Applicationsinstrumentation(defibrillators, etc.)● Materials and Design● Systems Manufacturing (i.e. PWB/PCB assembly, stacked packages)● Reliability/Safety/Regulatory/TestingThe abstract and presentation must benon-commercial in nature and emphasizethe medical technology and not thecompany portfolio. Please include yourcontact information (address, phonenumber, email address) and a presentationtitle with your abstract submission. Pleaseprovide an abstract of 300 wordsminimum on any of the topics above byemail to bcooper@meptec.org (for firstfour topics) or patti@smta.org (for lastfour topics). There is no technical paperrequirement for this symposium.Presentations are due on August 30, 2011.Chip Scale Review May/June 2011 [ChipScaleReview.com] 47

(continued from Page 26)Figure 6. TSV placement and assignment tominimize cost and maximize routabilitystacking can improve system performanceand not break the bank. However, it’s notenough to show that the system is routable,but that the physical layout can supportthe required data speeds. The ability toverify signal and power integrity over thecomplete 3D stack is thus the final essentialcomponent of the 3D pathfinding tool. Atrue-3D tool, which has all the connectivityand electrical information for the TSVsand 3D interconnects in place, is the idealengine for extracting the full parasiticnetwork of the 3D structure. In pathfindingmode, approximate algorithms aresufficient to provide confidence inperformance estimates; however, the sameengine can be used to provide the inputsto more detailed analyses as needed lateron in the flow.ConclusionBy choosing as an example a very basic2.5D design case to illustrate how a true-3D pathfinding tool can identify costsavings while re-using existing components,we wanted to show that it’s not necessaryto start from scratch and re-architect entirelynew systems to reap the benefits of 3Dintegration. This being said, one can onlyimagine how much more can be achievedby pushing the analysis to a finer level.The pain of 3D design comes largelyfrom the need to perform multipledifferent types of operations _partitioning, routing, extraction, etc _that heretofore required different tools,each having different file formats, andthat were not designed to supportmultiple technologies. A single true-3Dpathfinding tool, such as presented here,which does communicate gracefully withthe rest of the flow, is what is requiredto remove this pain.The fear of 3D design _ at least thatpart which is due to uncertainty in costand performance benefits _ comes fromhaving to take a leap of faith on inexactmodels at the front end of the design flow,not knowing if these will hold up by thetime it reaches the end. It is absolutelyvital to have a tool that can dive into thephysical design space at an early stage tovalidate the performance predictions andto provide accurate data for costmodeling. With such a tool in hand, thereis absolutely nothing left to stop anyonefrom seeing how they can profit from 3Dintegration.ADVERTISER-INDEXAries Electronics www.arieselec.com .................................................... 15Az Tech Direct www.aztechdirect.com ................................................... 26Crane Aerospace & Electronics www.craneae.com/microelec ................ 43DL Technology www.dltechnology.com .................................................. 11ECTC www.ectc.net ................................................................................ 46Essai www.essai.com .......................................................................... OBCE-tec Interconnect www.e-tec.com ........................................................ 47Everett Charles Technologies www.ectinfo.com/zip ..................... 35,37,39Hanmi Semiconductor www.hanmisemi.com ........................................ 2,3HCD Corp www.hcdcorp.com ................................................................. 23International Micro Industries www.imi-corp.com ................................. 32Indium Corp www.indium.us/E107 ......................................................... 19Ironwood Electronics www.ironwoodelectronics.com ............................. 47ISI www.isipkg.com ............................................................................... 21IWLPC www.iwlpc.com ............................................................................ 9Micro Control Company www.microcontrol.com ..................................... 1Nanium S.A. www.nanium.com ............................................................. 13Newport www.newport.com/bond1 ....................................................... IFCNordson Dage www.nordsondage.com ................................................... 41Pac Tech USA www.pactech-usa.com ............................................... 29,47Plastronics www.H-Pins.com .................................................................. 4Powertech Technology www.pti.com.tw .................................................. 7Quik-Pak www.icproto.com ..................................................................... 5RTI www.testfixtures.com ...................................................................... 45SEMI www.semi.org/events .................................................................. 36Sensata www.qinex.com ...................................................................... IBCTranscend Technologies www.modustest.com ................................. 25,4048 Chip Scale Review May/June 2011 [ChipScaleReview.com]ADVERTISING SALESWestern USA, EuropeReprintsKim Newman Chip Scale Review[knewman@chipscalereview.com]P.O. Box 9522 San Jose, CA 95157-0522T: 408.429.8585 F: 408.429.8605Central USA & Asia-PacificDirectory SalesRon Molnar AZ Tech Direct[rmolnar@chipscalereview.com]13801 S. 32nd Place Phoenix, AZ 85044T: 480.215.2654 F: 480.496.9451Eastern USARon Friedman [rfriedman@chipscalereview.com]P.O. Box 370183, W. Hartford, CT 06137T: 860.523.1105 F: 860.232.8337Austria-Germany-SwitzerlandSven Anacker IMP Intermedia Partners GmbH[sanacker@intermediapartners.de]In der Fleute 46, 42389 Wuppertal, GermanyT: +49.202.27169.17 F: +49.202.27169.20KoreaKeon Chang Young Media [ymedia@ymedia.co.kr]407 Jinyang Sangga, 120-3 Chungmuro 4 gaChung-ku, Seoul, Korea 100-863T: +82.2.2273.4819 F: +82.2.2273.4866