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PICBASIC PLUS LITE Manual - Profe Saul

PICBASIC PLUS LITE Manual - Profe Saul

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<strong>PICBASIC</strong> <strong>PLUS</strong> CompilerInf:LOW LEDDELAYMS 500HIGH LEDDELAYMS 500GOTO InfInitiating an interrupt.Before we can change any bits that correspond to interrupts we needto make sure that global interrupts are disabled. This is done by clearingthe GIE bit of INTCON (INTCON.7). Sometimes an interrupt mayoccur while the GIE bit is being cleared, which means that the bit isnot actually cleared and global interrupts are not disabled. To makesure that the GIE bit is actually cleared we must poll it. This can beaccomplished by a simple loop: -GIE = 0WHILE GIE = 1GIE = 0WEND‘ Disable global interrupts‘ Make sure they are off‘ Continue to clear GIE‘ Exit when GIE is clearThe prescaler attachment to TMR0 is controlled by bits 0:2 of the OP-TION_REG (PS0, 1, 2). The table below shows their relationship tothe prescaled ratio applied. But before the prescaler can be calculatedwe must inform the PIC as to what clock governs TMR0. This is doneby setting or clearing the PSA bit of OPTION_REG (OPTION_REG.3).If PSA is cleared then TMR0 is attached to the external crystal oscillator.If it is set then it is attached to the watchdog timer, which uses theinternal RC oscillator. This is important to remember; as the prescaleratio differs according to which oscillator it is attached to.PS2 PS1 PS0 PSA=0 (External crystal OSC) PSA=1 (Internal WDT OSC)0 0 0 1 : 2 1 : 10 0 1 1 : 4 1 : 20 1 0 1 : 8 1 : 40 1 1 1 : 16 1 : 81 0 0 1 : 32 1 : 161 0 1 1 : 64 1 : 321 1 0 1 : 128 1 : 641 1 1 1 : 256 1 : 128TMR0 prescaler ratio configurations.As can be seen from the above table, if we require TMR0 to incrementon every instruction cycle (4/OSC) we must clear PS2..0 and setPSA, which would attach it to the watchdog timer. This will cause aninterrupt to occur every 256us (assuming a 4MHz crystal). If the samevalues were placed into PS2..0 and PSA was cleared (attached to theexternal oscillator) then TMR0 would increment on every 2 nd instructioncycle and cause an interrupt to occur every 512us.80Copyright Crownhill 2001

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