Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host Bridge/DRAM Controller Registers (D0:F0) 4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 MMIO Range: MCHBAR Address Offset: 120–123h Default Value: 400028_00ssh (s = strap dependent) Access: RO, R/W Size: 32 bits Bit Access & Default 31:30 01b Reserved 29 R/W 0b 28:11 00h Reserved 10:8 R/W 000b 7 RO 0b Description Initialization Complete (IC): This bit is used for communication of the software state between the memory controller and BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is complete. Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000 = Refresh disabled 001 = Refresh enabled. Refresh interval 15.6 usec 010 = Refresh enabled. Refresh interval 7.8 usec 011 = Refresh enabled. Refresh interval 3.9 usec 100 = Refresh enabled. Refresh interval 1.95 usec 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other = Reserved Reserved 98 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Bit Access & Default 6:4 R/W 000b 3:2 Reserved 1:0 RO ss Host Bridge/DRAM Controller Registers (D0:F0) Description Mode Select (SMS): These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. 000 = Post Reset state – When the (G)MCH exits reset (power-up or otherwise), the mode select field is cleared to 000. During any reset sequence, while power is applied and reset is active, the (G)MCH de-asserts all CKE signals. After internal reset is de-asserted, CKE signals remain deasserted until this field is written to a value different than 000. On this event, all CKE signals are asserted. During suspend, (G)MCH internal signal triggers DRAM controller to flush pending commands and enter all ranks into Self-Refresh mode. As part of resume sequence, the (G)MCH will be reset, which will clear this bit field to 000 and maintain CKE signals de-asserted. After internal reset is de-asserted, the CKE signals remain de-asserted until this field is written to a value different than 000. On this event, all CKE signals are asserted. During entry to other low power states (C3, S1), the (G)MCH internal signal triggers the DRAM controller to flush pending commands and enter all ranks into Self-Refresh mode. During exit to normal mode, the (G)MCH signal triggers the DRAM controller to exit Self-Refresh and resume normal operation without software involvement. 001 = NOP Command Enable – All processor cycles to DRAM result in a NOP command on the DRAM interface. 010 = All Banks Pre-charge Enable – All processor cycles to DRAM result in an "all banks precharge" command on the DRAM interface. 011 = Mode Register Set Enable – All processor cycles to DRAM result in a "mode register" set command on the DRAM interface. Host address lines are mapped to DRAM address lines in order to specify the command sent, as shown in Volume 1, System Memory Controller section, memory Detection and Initialization. Refer to JEDEC Standard 79-2A Section 2.2.2 “Programming the Mode and Extended Mode Registers”. 100 = Extended Mode Register Set Enable – All processor cycles to DRAM result in an "extended mode register set" command on the DRAM interface. Host address lines are mapped to DRAM address lines in order to specify the command sent, as shown in Volume 1, System Memory Controller section, memory Detection and Initialization. Refer to JEDEC Standard 79-2A Section 2.2.2 “Programming the Mode and Extended Mode Registers”. 110 = CBR Refresh Enable – In this mode all processor cycles to DRAM result in a CBR cycle on the DRAM interface. 111 = Normal operation DRAM Type (DT): This field is used to select between supported SDRAM types. 00 = Reserved 01 = Reserved 10 = Second Revision Dual Data Rate (DDR2) SDRAM 11 = Reserved Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 99
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
- Page 59 and 60: Bit Access & Default 10:8 R/W 000b
- Page 61 and 62: Host Bridge/DRAM Controller Registe
- Page 63 and 64: 4.1 Device 0 Configuration Register
- Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
- Page 71 and 72: Host Bridge/DRAM Controller Registe
- Page 73 and 74: Host Bridge/DRAM Controller Registe
- Page 75 and 76: Host Bridge/DRAM Controller Registe
- Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
- Page 79 and 80: 4.1.21 PAM3—Programmable Attribut
- Page 81 and 82: 4.1.23 PAM5—Programmable Attribut
- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
- Page 85 and 86: Host Bridge/DRAM Controller Registe
- Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
- Page 89 and 90: 4.1.31 SKPD—Scratchpad Data (D0:F
- Page 91 and 92: Host Bridge/DRAM Controller Registe
- Page 93 and 94: Host Bridge/DRAM Controller Registe
- Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
- Page 97: 4.2.9 C0DRT1—Channel A DRAM Timin
- Page 101 and 102: Host Bridge/DRAM Controller Registe
- Page 103 and 104: 4.2.24 PMSTS—Power Management Sta
- Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
- Page 109 and 110: Host-PCI Express* Bridge Registers
- Page 111 and 112: Address Offset Host-PCI Express* Br
- Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
- Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
- Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
- Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
- Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
- Page 123 and 124: Host-PCI Express* Bridge Registers
- Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
- Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
- Page 129 and 130: Host-PCI Express* Bridge Registers
- Page 131 and 132: Host-PCI Express* Bridge Registers
- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
- Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
- Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
- Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
- Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
- Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
- Page 147 and 148: Host-PCI Express* Bridge Registers
Host Bridge/DRAM Controller Registers (D0:F0)<br />
4.2.10 C0DRC0—Channel A DRAM Controller Mode 0<br />
MMIO Range: MCHBAR<br />
Address Offset: 120–123h<br />
Default Value: 400028_00ssh (s = strap dependent)<br />
Access: RO, R/W<br />
Size: 32 bits<br />
Bit<br />
Access &<br />
Default<br />
31:30 01b Reserved<br />
29 R/W<br />
0b<br />
28:11 00h Reserved<br />
10:8 R/W<br />
000b<br />
7 RO<br />
0b<br />
Description<br />
Initialization Complete (IC): This bit is used for communication of the software<br />
state between the memory controller and BIOS. BIOS sets this bit to 1 after<br />
initialization of the DRAM memory array is complete.<br />
Refresh Mode Select (RMS): This field determines whether refresh is enabled<br />
and, if so, at what rate refreshes will be executed.<br />
000 = Refresh disabled<br />
001 = Refresh enabled. Refresh interval 15.6 usec<br />
010 = Refresh enabled. Refresh interval 7.8 usec<br />
011 = Refresh enabled. Refresh interval 3.9 usec<br />
100 = Refresh enabled. Refresh interval 1.95 usec<br />
111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode)<br />
Other = Reserved<br />
Reserved<br />
98 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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