Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

4.2.7 C0DCLKDIS—Channel A DRAM Clock Disable
MMIO Range: MCHBAR
Address Offset: 10Ch
Default Value: 00h
Access: R/W
Size: 8 bits
Host Bridge/DRAM Controller Registers (D0:F0)
This register can be used to disable the system memory clock signals to each DIMM slot, which
can significantly reduce EMI and power concerns for clocks that go to unpopulated DIMMs.
Clocks should be enabled based on whether a slot is populated, and what kind of DIMM is
present.
Note: Since there are multiple clock signals assigned to each rank of a DIMM, it is important to clarify
exactly which rank width field affects which clock signal.
Bit Access &
Default
7:6 Reserved
5 R/W
0b
4 R/W
0b
3 R/W
0b
2 R/W
0b
1 R/W
0b
0 R/W
0b
DIMM Clock Gate Enable Pair 5:
Description
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
DIMM Clock Gate Enable Pair 4:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
DIMM Clock Gate Enable Pair 3:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
DIMM Clock Gate Enable Pair 2:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
DIMM Clock Gate Enable Pair 1:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
DIMM Clock Gate Enable Pair 0:
0 = Tri-state the corresponding clock pair.
1 = Enable the corresponding clock pair.
Channel Rank Clocks Affected
0 0 or 1 SCLK_A[2:0]/ SCLK_A[2:0]#
0 2 or 3 SCLK_A[5:3]/ SCLK_A[5:3]#
1 0 or 1 SCLK_B[2:0]/ SCLK_B[2:0]#
1 2 or 3 SCLK_B[5:3]/ SCLK_B[5:3]#
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 95