Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Host Bridge/DRAM Controller Registers (D0:F0) Interleaved Channels Example If channels are interleaved, corresponding ranks in opposing channels will contain the same value, and the value programmed takes into account the fact that twice as many addresses are spanned by this rank compared to the single-channel case. With interleaved channels, a value of 01h in C0DRB0 and a value of 01h in C1DRB0 indicate that 32 MB of DRAM has been populated in the first rank of each channel and the top address in that rank of either channel is 64 MB. Programming guide: C0DRB0 = C1DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 = C1DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments) –––– C0DRB3 = C1DRB3 = Total memory in chA rank0 + chA rank1+ chA rank2 + chA rank3 (in 32-MB increments) In all modes, if a DIMM is single sided, it appears as a populated rank and an empty rank. A DRB must be programmed appropriately for each mode. Each Rank is represented by a byte. Each byte has the following format. Bit Access & Default 7:0 R/W 00h Description Channel A DRAM Rank Boundary Address: This 8 bit value defines the upper and lower addresses for each DRAM rank. Bits 6:2 are compared against Address 31:27 to determine the upper address limit of a particular rank. Bits 1:0 must be 0s. For the 82945G and 82945P, bit 7 may be programmed to a 1 in the highest DRB (DRB3) if 4 GBs of memory are present. 92 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0) 4.2.2 C0DRB1—Channel A DRAM Rank Boundary Address 1 MMIO Range: MCHBAR Address Offset: 101h Default Value: 00h Access: R/W Size: 8 bits The operation of this register is detailed in the description for the C0DRB0 register. 4.2.3 C0DRB2—Channel A DRAM Rank Boundary Address 2 MMIO Range: MCHBAR Address Offset: 102h Default Value: 00h Access: R/W Size: 8 bits The operation of this register is detailed in the description for the C0DRB0 register. 4.2.4 C0DRB3—Channel A DRAM Rank Boundary Address 3 MMIO Range: MCHBAR Address Offset: 103h Default Value: 00h Access: R/W Size: 8 bits The operation of this register is detailed in the description for the C0DRB0 register. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 93
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
Page 43 and 44: 2.10 Power and Ground Name Voltage
Page 45 and 46: Interface Signal Name I/O System Me
Page 47 and 48: Interface Signal Name I/O State Dur
Page 49 and 50: 3 Register Description Register Des
Page 51 and 52: Register Description Note: A physic
Page 53 and 54: 3.3 Configuration Mechanisms Regist
Page 55 and 56: 3.4 Routing Configuration Accesses
Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
Page 59 and 60: Bit Access & Default 10:8 R/W 000b
Page 61 and 62: Host Bridge/DRAM Controller Registe
Page 63 and 64: 4.1 Device 0 Configuration Register
Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
Page 83 and 84: 4.1.25 LAC—Legacy Access Control
Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
Page 89 and 90: 4.1.31 SKPD—Scratchpad Data (D0:F
Page 91: Host Bridge/DRAM Controller Registe
Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
Page 97 and 98: 4.2.9 C0DRT1—Channel A DRAM Timin
Page 99 and 100: Bit Access & Default 6:4 R/W 000b 3
Page 103 and 104: 4.2.24 PMSTS—Power Management Sta
Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
Page 109 and 110: Host-PCI Express* Bridge Registers
Page 111 and 112: Address Offset Host-PCI Express* Br
Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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Host-PCI Express* Bridge Registers
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5.1.56 ESD—Element Self Descripti
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5.1.61 CESTS—Correctable Error St
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Direct Media Interface (DMI) RCRB 6
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6.1.3 DMIPVCCAP2—DMI Port VC Capa
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6.1.6 DMIVC0RCTL—DMI VC0 Resource
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6.1.9 DMIVC1RCTL—DMI VC1 Resource
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6.1.13 DMILSTS—DMI Link Status MM
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6.1.15 DMIUEMSK—DMI Uncorrectable
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Integrated Graphics Device (D2:F0)
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7.1.4 PCISTS2—PCI Status (D2:F0)
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7.1.7 CLS—Cache Line Size (D2:F0)
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7.1.11 IOBAR—I/O Base Address (D2
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7.1.20 MINGNT—Minimum Grant (D2:F
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8.1.3 PCICMD2—PCI Command (D2:F1)
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8.1.5 RID2—Revision Identificatio
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8.2 Device 2 - PCI I/O Registers In
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9 System Address Map System Address
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Figure 9-1. System Address Ranges 4
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Compatible SMRAM Address Range (A_0
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9.2 Main Memory Address Range (1 MB
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9.3 PCI Memory Address Range (TOLUD
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9.3.6 PCI Express* Graphics Attach
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9.4.1 SMM Space Definition System A
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9.4.5 SMM Space Decode and Transact
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9.4.12 Legacy VGA and I/O Range Dec
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10 Functional Description This chap
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Interleaved Mode Functional Descrip
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667 MHz (PC 5300) (82945G/82945GC/8
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10.2.2.2 System Memory Supported Co
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Functional Description Table 10-5.
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10.3 PCI Express* (Intel ® 82945G/
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Figure 10-2. SDVO Conceptual Block
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Figure 10-3. Concurrent SDVO / PCI
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10.5 Integrated Graphics Device (In
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10.5.3 4X Faster Setup Engine Funct
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10.5.4 Texture Engine Functional De
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10.5.4.8 Pixel Shader Functional De
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Functional Description to determine
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10.5.6 2D Engine Functional Descrip
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10.5.8.1 Cursor Plane Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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