Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

intel
16.08.2012 Views

Host Bridge/DRAM Controller Registers (D0:F0) 4.2 MCHBAR Register The MCHBAR registers are offset from the MCHBAR base address. Table 4-2 provides an address map of the registers listed by address offset in ascending order. Detailed register bit descriptions follow the table. Table 4-2. MCHBAR Register Address Map Address Offset Symbol Register Name Default Value Access 100h C0DRB0 Channel A DRAM Rank Boundary Address 0 00h R/W 101h C0DRB1 Channel A DRAM Rank Boundary Address 1 00h R/W 102h C0DRB2 Channel A DRAM Rank Boundary Address 2 00h R/W 103h C0DRB3 Channel A DRAM Rank Boundary Address 3 00h R/W 108h C0DRA0 Channel A DRAM Rank 0,1 Attribute 00h RO, R/W 109h C0DRA2 Channel A DRAM Rank 2,3 Attribute 00h RO, R/W 10Ch C0DCLKDIS Channel A DRAM Clock Disable 00h RO, R/W 10E–10Fh C0BNKARC Channel A DRAM Bank Architecture 0000h RO, R/W 114–117h C0DRT1 Channel A DRAM Timing Register 1 02903D22h R/W, RO 120–123h C0DRC0 Channel A DRAM Controller Mode 0 4000280_ 00ssh RO, R/W 124–127h C0DRC1 Channel A DRAM Controller Mode 1 00000000h R/W 180h C1DRB0 Channel B DRAM Rank Boundary Address 0 00h R/W 181h C1DRB1 Channel B DRAM Rank Boundary Address 1 00h R/W 182h C1DRB2 Channel B DRAM Rank Boundary Address 2 00h R/W 183h C1DRB3 Channel B DRAM Rank Boundary Address 3 00h R/W 188h C1DRA0 Channel B DRAM Rank 0,1 Attribute 00h RO, R/W 189h C1DRA2 Channel B DRAM Rank 2,3 Attribute 00h RO, R/W 18Ch C1DCLKDIS Channel B DRAM Clock Disable 00h RO, R/W/L 18E–18Fh C1BNKARC Channel B Bank Architecture 0000h RO, R/W 194–197h C1DRT1 Channel B DRAM Timing Register 1 02903D22h RO 1A0–1A3h C1DRC0 Channel B DRAM Controller Mode 0 4000280_ 00ssh RO, R/W 1A4–1A7h C1DRC1 Channel B DRAM Controller Mode 1 00000000h R/W, RO, R/W/L F10–F13h PMCFG Power Management Configuration 00000000h R/W, RO F14–F17h PMSTS Power Management Status 00000000h R/WC/S 90 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet

Host Bridge/DRAM Controller Registers (D0:F0) 4.2.1 C0DRB0—Channel A DRAM Rank Boundary Address 0 MMIO Range: MCHBAR Address Offset: 100h Default Value: 00h Access: R/W Size: 8 bits The DRAM Rank Boundary register defines the upper boundary address of each DRAM rank with a granularity of 32 MB. Each rank has its own single-byte DRB register. These registers are used to determine which chip select will be active for a given address. Channel and rank map: Channel A Rank 0: 100h Channel A Rank 1: 101h Channel A Rank 2: 102h Channel A Rank 3: 103h Channel B Rank 0: 180h Channel B Rank 1: 181h Channel B Rank 2: 182h Channel B Rank 3: 183h Single Channel or Asymmetric Channels Example If the channels are independent, addresses in Channel B should begin where addresses in Channel A left off, and the address of the first rank of Channel A can be calculated from the technology (256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and the top address in that rank is 32 MB. Programming guide: If Channel A is empty, all of the C0DRBs are programmed with 00h. C0DRB0 = Total memory in chA rank0 (in 32-MB increments) C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments) –––– C1DRB0 = Total memory in chA rank0 + chA rank1 + chA rank2 + chA rank3 + chB rank0 (in 32-MB increments) If Channel B is empty, all of the C1DRBs are programmed with the same value as C0DRB3. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 91

Host Bridge/DRAM Controller Registers (D0:F0)<br />

4.2.1 C0DRB0—Channel A DRAM Rank Boundary Address 0<br />

MMIO Range: MCHBAR<br />

Address Offset: 100h<br />

Default Value: 00h<br />

Access: R/W<br />

Size: 8 bits<br />

The DRAM Rank Boundary register defines the upper boundary address of each DRAM rank<br />

with a granularity of 32 MB. Each rank has its own single-byte DRB register. These registers are<br />

used to determine which chip select will be active for a given address.<br />

Channel and rank map:<br />

Channel A Rank 0: 100h<br />

Channel A Rank 1: 101h<br />

Channel A Rank 2: 102h<br />

Channel A Rank 3: 103h<br />

Channel B Rank 0: 180h<br />

Channel B Rank 1: 181h<br />

Channel B Rank 2: 182h<br />

Channel B Rank 3: 183h<br />

Single Channel or Asymmetric Channels Example<br />

If the channels are independent, addresses in Channel B should begin where addresses in Channel<br />

A left off, and the address of the first rank of Channel A can be calculated from the technology<br />

(256 Mbit, 512 Mbit, or 1 Gbit) and the x8 or x16 configuration. With independent channels, a<br />

value of 01h in C0DRB0 indicates that 32 MB of DRAM has been populated in the first rank, and<br />

the top address in that rank is 32 MB.<br />

Programming guide:<br />

If Channel A is empty, all of the C0DRBs are programmed with 00h.<br />

C0DRB0 = Total memory in chA rank0 (in 32-MB increments)<br />

C0DRB1 = Total memory in chA rank0 + chA rank1 (in 32-MB increments)<br />

––––<br />

C1DRB0 = Total memory in chA rank0 + chA rank1 + chA rank2 + chA rank3 + chB rank0<br />

(in 32-MB increments)<br />

If Channel B is empty, all of the C1DRBs are programmed with the same value as C0DRB3.<br />

Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 91

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