Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4.2 MCHBAR Register
The MCHBAR registers are offset from the MCHBAR base address. Table 4-2 provides an
address map of the registers listed by address offset in ascending order. Detailed register bit
descriptions follow the table.
Table 4-2. MCHBAR Register Address Map
Address
Offset
Symbol Register Name Default
Value
Access
100h C0DRB0 Channel A DRAM Rank Boundary Address 0 00h R/W
101h C0DRB1 Channel A DRAM Rank Boundary Address 1 00h R/W
102h C0DRB2 Channel A DRAM Rank Boundary Address 2 00h R/W
103h C0DRB3 Channel A DRAM Rank Boundary Address 3 00h R/W
108h C0DRA0 Channel A DRAM Rank 0,1 Attribute 00h RO, R/W
109h C0DRA2 Channel A DRAM Rank 2,3 Attribute 00h RO, R/W
10Ch C0DCLKDIS Channel A DRAM Clock Disable 00h RO, R/W
10E–10Fh C0BNKARC Channel A DRAM Bank Architecture 0000h RO, R/W
114–117h C0DRT1 Channel A DRAM Timing Register 1 02903D22h R/W, RO
120–123h C0DRC0 Channel A DRAM Controller Mode 0 4000280_
00ssh
RO, R/W
124–127h C0DRC1 Channel A DRAM Controller Mode 1 00000000h R/W
180h C1DRB0 Channel B DRAM Rank Boundary Address 0 00h R/W
181h C1DRB1 Channel B DRAM Rank Boundary Address 1 00h R/W
182h C1DRB2 Channel B DRAM Rank Boundary Address 2 00h R/W
183h C1DRB3 Channel B DRAM Rank Boundary Address 3 00h R/W
188h C1DRA0 Channel B DRAM Rank 0,1 Attribute 00h RO, R/W
189h C1DRA2 Channel B DRAM Rank 2,3 Attribute 00h RO, R/W
18Ch C1DCLKDIS Channel B DRAM Clock Disable 00h RO, R/W/L
18E–18Fh C1BNKARC Channel B Bank Architecture 0000h RO, R/W
194–197h C1DRT1 Channel B DRAM Timing Register 1 02903D22h RO
1A0–1A3h C1DRC0 Channel B DRAM Controller Mode 0 4000280_
00ssh
RO, R/W
1A4–1A7h C1DRC1 Channel B DRAM Controller Mode 1 00000000h R/W, RO,
R/W/L
F10–F13h PMCFG Power Management Configuration 00000000h R/W, RO
F14–F17h PMSTS Power Management Status 00000000h R/WC/S
90 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet