Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host Bridge/DRAM Controller Registers (D0:F0) 4.1.30 ERRCMD—Error Command (D0:F0) PCI Device: 0 Address Offset: CAh Default Value: 0000h Access: R/W Size: 16 bits This register controls the (G)MCH responses to various system errors. Since the (G)MCH does not have a SERR# signal, SERR messages are passed from the (G)MCH to the ICH7 over DMI. When a bit in this register is set, a SERR message will be generated on DMI when the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device 0 via the PCI Command register. Bit Access & Default 15:12 Reserved 11 R/W 0b 10 Reserved 9 R/W 0b 8 R/W 0b 7:0 Reserved Description SERR on (G)MCH Thermal Sensor Event (TSESERR) 1 = Enable. The (G)MCH generates a DMI SERR special cycle when bit 11 of the ERRSTS register is set. The SERR must not be enabled at the same time as the SMI for the same thermal sensor event. 0 = Disable. Reporting of this condition via SERR messaging is disabled. SERR on LOCK to non-DRAM Memory (LCKERR) 1 = Enable. The (G)MCH will generate a DMI SERR special cycle when a processor lock cycle is detected that does not hit DRAM. 0 = Disable. Reporting of this condition via SERR messaging is disabled. SERR on DRAM Refresh Timeout (DRTOERR) 1 = Enable. The (G)MCH generates a DMI SERR special cycle when a DRAM Refresh timeout occurs. 0 = Disable. Reporting of this condition via SERR messaging is disabled. 88 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
4.1.31 SKPD—Scratchpad Data (D0:F0) PCI Device: 0 Address Offset: DCh Default Value: 00000000h Access: R/W Size: 32 bits Host Bridge/DRAM Controller Registers (D0:F0) This register holds 32 writable bits with no functionality behind them. It is for the convenience of BIOS and graphics drivers. Bit Access & Default 31:0 R/W 00000000 h Description Scratchpad Data: 1 DWord of data storage. 4.1.32 CAPID0—Capability Identifier (D0:F0) PCI Device: 0 Address Offset: E0h Default Value: 82945G/82945GC/82945GZ GMCH: 000000000001090009h 82945P/82945PL MCH: 000000000001090009h Access: RO Size: 72 bits Bit Access & Default 71:28 Reserved 27:24 RO 1h 23:16 RO 09h 15:8 RO 00h 7:0 RO 09h Description CAPID Version: This field has the value 0001b to identify the first revision of the CAPID register definition. CAPID Length: This field has the value 09h to indicate the structure length (9 bytes). Next Capability Pointer: This field is hardwired to 00h indicating the end of the capabilities linked list. CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 89
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39 and 40: Signal Description 2.6 Analog Displ
- Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
- Page 59 and 60: Bit Access & Default 10:8 R/W 000b
- Page 61 and 62: Host Bridge/DRAM Controller Registe
- Page 63 and 64: 4.1 Device 0 Configuration Register
- Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
- Page 71 and 72: Host Bridge/DRAM Controller Registe
- Page 73 and 74: Host Bridge/DRAM Controller Registe
- Page 75 and 76: Host Bridge/DRAM Controller Registe
- Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
- Page 79 and 80: 4.1.21 PAM3—Programmable Attribut
- Page 81 and 82: 4.1.23 PAM5—Programmable Attribut
- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
- Page 85 and 86: Host Bridge/DRAM Controller Registe
- Page 87: 4.1.29 ERRSTS—Error Status (D0:F0
- Page 91 and 92: Host Bridge/DRAM Controller Registe
- Page 93 and 94: Host Bridge/DRAM Controller Registe
- Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
- Page 97 and 98: 4.2.9 C0DRT1—Channel A DRAM Timin
- Page 99 and 100: Bit Access & Default 6:4 R/W 000b 3
- Page 101 and 102: Host Bridge/DRAM Controller Registe
- Page 103 and 104: 4.2.24 PMSTS—Power Management Sta
- Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
- Page 109 and 110: Host-PCI Express* Bridge Registers
- Page 111 and 112: Address Offset Host-PCI Express* Br
- Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
- Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
- Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
- Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
- Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
- Page 123 and 124: Host-PCI Express* Bridge Registers
- Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
- Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
- Page 129 and 130: Host-PCI Express* Bridge Registers
- Page 131 and 132: Host-PCI Express* Bridge Registers
- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
- Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
4.1.31 SKPD—Scratchpad Data (D0:F0)<br />
PCI Device: 0<br />
Address Offset: DCh<br />
Default Value: 00000000h<br />
Access: R/W<br />
Size: 32 bits<br />
Host Bridge/DRAM Controller Registers (D0:F0)<br />
This register holds 32 writable bits with no functionality behind them. It is for the convenience of<br />
BIOS and graphics drivers.<br />
Bit Access &<br />
Default<br />
31:0 R/W<br />
00000000 h<br />
Description<br />
Scratchpad Data: 1 DWord of data storage.<br />
4.1.32 CAPID0—Capability Identifier (D0:F0)<br />
PCI Device: 0<br />
Address Offset: E0h<br />
Default Value: 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH:<br />
000000000001090009h<br />
82<strong>945P</strong>/82<strong>945P</strong>L MCH: 000000000001090009h<br />
Access: RO<br />
Size: 72 bits<br />
Bit Access &<br />
Default<br />
71:28 Reserved<br />
27:24 RO<br />
1h<br />
23:16 RO<br />
09h<br />
15:8 RO<br />
00h<br />
7:0 RO<br />
09h<br />
Description<br />
CAPID Version: This field has the value 0001b to identify the first revision of the<br />
CAPID register definition.<br />
CAPID Length: This field has the value 09h to indicate the structure length<br />
(9 bytes).<br />
Next Capability Pointer: This field is hardwired to 00h indicating the end of the<br />
capabilities linked list.<br />
CAP_ID: This field has the value 1001b to identify the CAP_ID assigned by the<br />
PCI SIG for vendor dependent capability pointers.<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 89
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