Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.30 ERRCMD—Error Command (D0:F0)
PCI Device: 0
Address Offset: CAh
Default Value: 0000h
Access: R/W
Size: 16 bits
This register controls the (G)MCH responses to various system errors. Since the (G)MCH does
not have a SERR# signal, SERR messages are passed from the (G)MCH to the ICH7 over DMI.
When a bit in this register is set, a SERR message will be generated on DMI when the
corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is
globally enabled for Device 0 via the PCI Command register.
Bit Access &
Default
15:12 Reserved
11 R/W
0b
10 Reserved
9 R/W
0b
8 R/W
0b
7:0 Reserved
Description
SERR on (G)MCH Thermal Sensor Event (TSESERR)
1 = Enable. The (G)MCH generates a DMI SERR special cycle when bit 11 of the
ERRSTS register is set. The SERR must not be enabled at the same time as
the SMI for the same thermal sensor event.
0 = Disable. Reporting of this condition via SERR messaging is disabled.
SERR on LOCK to non-DRAM Memory (LCKERR)
1 = Enable. The (G)MCH will generate a DMI SERR special cycle when a
processor lock cycle is detected that does not hit DRAM.
0 = Disable. Reporting of this condition via SERR messaging is disabled.
SERR on DRAM Refresh Timeout (DRTOERR)
1 = Enable. The (G)MCH generates a DMI SERR special cycle when a DRAM
Refresh timeout occurs.
0 = Disable. Reporting of this condition via SERR messaging is disabled.
88 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet