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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Host Bridge/DRAM Controller Registers (D0:F0)<br />

4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0)<br />

PCI Device: 0<br />

Address Offset: 9Ch<br />

Default Value: 08h<br />

Access: R/W<br />

Size: 8 bits<br />

This register defines the Top of Low usable DRAM. TSEG and graphics stolen memory are<br />

within the DRAM space defined. From the top of the DRAM space, the (G)MCH optionally<br />

claims 1 to 8 MBs of DRAM for internal graphics if enabled, and 1, 2, or 8 MB of DRAM for<br />

TSEG if enabled.<br />

Bit Access &<br />

Default<br />

7:3 R/W<br />

01h<br />

Description<br />

Top of Low Usable DRAM (TOLUD): This register contains bits 31:27 of an<br />

address one byte above the maximum DRAM memory that is usable by the<br />

operating system. Address bits 31:27 programmed to 01h implies a minimum<br />

memory size of 128 MBs.<br />

Configuration software must set this value to the smaller of the following 2 choices:<br />

� Maximum amount of memory in the system plus one byte or<br />

� Minimum address allocated for PCI memory<br />

Address bits 26:0 are assumed to be 000_0000h for the purposes of address<br />

comparison. The Host interface positively decodes an address intended for DRAM<br />

if the incoming address is less than the value programmed in this register.<br />

If this register is set to 0000 0b, it implies 128 MBs of system memory.<br />

2:0<br />

NOTE: The Top of Low Usable memory is the lowest address above both graphics<br />

stolen memory and TSEG. The host interface determines the base of<br />

graphics stolen memory by subtracting the Graphics Stolen Memory Size<br />

from TOLUD and further decrements by 1 MB to determine the base of<br />

TSEG.<br />

Reserved<br />

Programming Example (82<strong>945G</strong> GMCH only):<br />

� C1DRB7 is set to 4 GB<br />

� TSEG is enabled and TSEG size is set to 1 MB<br />

� Internal graphics is enabled and Graphics Mode Select is set to 32 MB<br />

� BIOS knows the OS requires 1GB of PCI space.<br />

BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This<br />

20-MB range at the very top of addressable memory space is lost to APIC.<br />

According to the above equation, TOLUD is originally calculated to: 4 GB = 1_0000_0000h<br />

The system memory requirements are:<br />

� 4 GB (max addressable space) – 1 GB (PCI space) – 20 MB (lost memory) =<br />

3 GB – 128 MB (minimum granularity) = B800_0000h<br />

� Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h; TOLUD<br />

should be programmed to B8h.<br />

84 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet

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