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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Host Bridge/DRAM Controller Registers (D0:F0)<br />

4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0)<br />

PCI Device: 0<br />

Address Offset: 96h<br />

Default Value: 00h<br />

Access: R/W<br />

Size: 8 bits<br />

This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h–<br />

0EFFFFh.<br />

Bit Access &<br />

Default<br />

7:6 Reserved<br />

5:4 R/W<br />

00b<br />

3:2 Reserved<br />

1:0 R/W<br />

00b<br />

Description<br />

0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of<br />

read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.<br />

00 = DRAM Disabled: Accesses are directed to the DMI.<br />

01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the<br />

DMI.<br />

10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.<br />

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.<br />

0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of<br />

read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.<br />

00 = DRAM Disabled: Accesses are directed to the DMI.<br />

01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the<br />

DMI.<br />

10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.<br />

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.<br />

82 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet

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