Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0)
PCI Device: 0
Address Offset: 94h
Default Value: 00h
Access: R/W
Size: 8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h–
0DFFFFh.
Bit Access &
Default
7:6 Reserved
5:4 R/W
00 b
3:2 Reserved
1:0 R/W
00 b
Description
0DC000h–0DFFFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0DC000h to 0DFFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
0D8000h–0DBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D8000h to 0DBFFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
80 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet