Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
8.1.11 SVID2—Subsystem Vendor Identification (D2:F1) ............................. 197 8.1.12 SID2—Subsystem Identification (D2:F1) ............................................ 197 8.1.13 ROMADR—Video BIOS ROM Base Address (D2:F1) ....................... 198 8.1.14 CAPPOINT—Capabilities Pointer (D2:F1) ......................................... 198 8.1.15 MINGNT—Minimum Grant Register (D2:F1) ...................................... 198 8.1.16 MAXLAT—Maximum Latency (D2:F1) ............................................... 198 8.1.17 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F1) (Mirrored_D0_34) ............................................................................... 199 8.1.18 MCAPID—Mirror of Device 0 Capability Identification (D2:F1) (Mirrored_D0_E0) ............................................................................... 199 8.1.19 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F1) (Mirrored_D0_52) ............................................................................... 199 8.1.20 MDEVEN—Mirror of Device 0 Device Enable (D2:F1) (Mirrored_D0_54) ............................................................................... 199 8.1.21 BSM—Base of Stolen Memory Register (D2:F1) ............................... 200 8.1.22 PMCAPID—Power Management Capabilities ID (D2:F1) .................. 200 8.1.23 PMCAP—Power Management Capabilities (D2:F1) .......................... 200 8.1.24 PMCS—Power Management Control/Status (D2:F1) ........................ 201 8.1.25 SWSMI—Software SMI (D2:F1) ......................................................... 201 8.1.26 ASLS—ASL Storage (D2:F1) ............................................................. 202 8.2 Device 2 – PCI I/O Registers ............................................................................. 203 8.2.1 MMIO Index—MMIO Address Register .............................................. 203 8.2.2 MMIO Data—MMIO Data Register ..................................................... 203 9 System Address Map ...................................................................................................... 205 9.1 Legacy Address Range ...................................................................................... 207 9.1.1 DOS Range (0h – 9_FFFFh) .............................................................. 208 9.1.2 Legacy Video Area (A_0000h–B_FFFFh) .......................................... 208 9.1.3 Expansion Area (C_0000h–D_FFFFh) ............................................... 209 9.1.4 Extended System BIOS Area (E_0000h–E_FFFFh) .......................... 210 9.1.5 System BIOS Area (F_0000h–F_FFFFh) ........................................... 210 9.1.6 Programmable Attribute Map (PAM) Memory Area Details ................ 210 9.2 Main Memory Address Range (1 MB to TOLUD) .............................................. 211 9.2.1 ISA Hole (15 MB–16 MB) ................................................................... 212 9.2.2 TSEG .................................................................................................. 212 9.2.3 Pre-allocated Memory ......................................................................... 212 9.3 PCI Memory Address Range (TOLUD – 4 GB) ................................................. 213 9.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ................. 214 9.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ................................................ 214 9.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................ 214 9.3.4 High BIOS Area .................................................................................. 214 9.3.5 PCI Express* Configuration Address Space ...................................... 214 9.3.6 PCI Express* Graphics Attach (Intel ® 82945G/82945GC/82945P/82945PL GMCH Only) ............................ 215 9.3.7 AGP DRAM Graphics Aperture .......................................................... 215 9.3.8 Graphics Memory Address Ranges (Intel ® 82945G/82945GC/82945GZ GMCH Only) ....................................................................................... 216 9.4 System Management Mode (SMM) ................................................................... 216 9.4.1 SMM Space Definition ........................................................................ 217 9.4.2 SMM Space Restrictions .................................................................... 217 9.4.3 SMM Space Combinations ................................................................. 218 9.4.4 SMM Control Combinations ................................................................ 218 8 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
9.4.5 SMM Space Decode and Transaction Handling ................................ 219 9.4.6 Processor WB Transaction to an Enabled SMM Address Space ...... 219 9.4.7 SMM Access through GTT TLB (Intel ® 82945G/82945GC/82945GZ GMCH Only) ....................................................................................... 219 9.4.8 Memory Shadowing ............................................................................ 219 9.4.9 I/O Address Space .............................................................................. 220 9.4.10 PCI Express* I/O Address Mapping ................................................... 220 9.4.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping ............ 220 9.4.12 Legacy VGA and I/O Range Decode Rules ....................................... 221 10 Functional Description .................................................................................................... 223 10.1 Host Interface ..................................................................................................... 223 10.1.1 FSB IOQ Depth ................................................................................... 223 10.1.2 FSB OOQ Depth ................................................................................. 223 10.1.3 FSB GTL+ Termination ....................................................................... 223 10.1.4 FSB Dynamic Bus Inversion ............................................................... 223 10.1.4.1 APIC Cluster Mode Support .............................................. 224 10.2 System Memory Controller ................................................................................. 224 10.2.1 System Memory Configuration Registers Overview ........................... 226 10.2.2 DRAM Technologies and Organization .............................................. 226 10.2.2.1 Rules for Populating DIMM Slots ...................................... 228 10.2.2.2 System Memory Supported Configurations ...................... 229 10.2.2.3 Main Memory DRAM Address Translation and Decoding 229 10.2.3 DRAM Clock Generation .................................................................... 232 10.2.4 Suspend to RAM and Resume ........................................................... 232 10.2.5 DDR2 On Die Termination .................................................................. 232 10.3 PCI Express* (Intel ® 82945G/82945GC/ 82945P/82945PL (G)MCH Only) ...... 233 10.3.1 Transaction Layer ............................................................................... 233 10.3.2 Data Link Layer ................................................................................... 233 10.3.3 Physical Layer ..................................................................................... 233 10.4 Intel ® Serial Digital Video Output (SDVO) (Intel ® 82945G/82945GC/82945GZ GMCH Only) ....................................................................................................... 234 10.4.1 Intel ® SDVO Capabilities..................................................................... 234 10.4.2 Intel ® SDVO Modes ............................................................................ 235 10.4.3 PCI Express* and Internal Graphics Simultaneous Operation (Intel ® 82945G/82945GC GMCH Only) ......................................................... 236 10.4.3.1 Standard PCI Express * Cards and Internal Graphics ....... 236 10.4.3.2 ADD2+ Cards (Concurrent SDVO and PCI Express*) ...... 236 10.5 Integrated Graphics Device (Intel ® 82945G/82945GC/82945GZ GMCH Only) 239 10.5.1 3D Graphics Pipeline .......................................................................... 239 10.5.2 3D Engine ........................................................................................... 240 10.5.3 4X Faster Setup Engine ...................................................................... 241 10.5.3.1 3D Primitives and Data Formats Support .......................... 241 10.5.3.2 Pixel Accurate “Fast” Scissoring and Clipping Operation . 241 10.5.3.3 Depth Bias ......................................................................... 241 10.5.3.4 Backface Culling ................................................................ 242 10.5.3.5 Scan Converter .................................................................. 242 10.5.3.6 Pixel Rasterization Rules .................................................. 242 10.5.3.7 Pixel Pipeline ..................................................................... 242 10.5.3.8 Texture Samplers .............................................................. 242 10.5.3.9 2D Functionality ................................................................. 242 10.5.4 Texture Engine .................................................................................... 243 Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 9
- Page 1 and 2: Intel ® 945G/945GZ/945GC/ 945P/945
- Page 3 and 4: Contents 1 Introduction ...........
- Page 5 and 6: 4.2.11 C0DRC1—Channel A DRAM Cont
- Page 7: 6.1.16 DMICESTS—DMI Correctable E
- Page 11 and 12: 11.3 DC Characteristics ...........
- Page 13 and 14: Revision History Rev Description Da
- Page 15 and 16: Intel ® 82945G/82945GZ/82945GC/829
- Page 17 and 18: 1 Introduction Introduction The Int
- Page 19 and 20: Figure 1-2. Intel ® 945GZ/82945GC
- Page 21 and 22: 1.1 Terminology Term Description Ac
- Page 23 and 24: Term Description TOLM Top Of Low Me
- Page 25 and 26: Introduction � Supports four bank
- Page 27 and 28: Introduction 1.4 Graphics (Intel ®
- Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
- Page 31 and 32: 2 Signal Description Signal Descrip
- Page 33 and 34: 2.1 Host Interface Signals Signal D
- Page 35 and 36: Signal Name Type Description HREQ[4
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39 and 40: Signal Description 2.6 Analog Displ
- Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
8.1.11 SVID2—Subsystem Vendor Identification (D2:F1) ............................. 197<br />
8.1.12 SID2—Subsystem Identification (D2:F1) ............................................ 197<br />
8.1.13 ROMADR—Video BIOS ROM Base Address (D2:F1) ....................... 198<br />
8.1.14 CAPPOINT—Capabilities Pointer (D2:F1) ......................................... 198<br />
8.1.15 MINGNT—Minimum Grant Register (D2:F1) ...................................... 198<br />
8.1.16 MAXLAT—Maximum Latency (D2:F1) ............................................... 198<br />
8.1.17 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F1)<br />
(Mirrored_D0_34) ............................................................................... 199<br />
8.1.18 MCAPID—Mirror of Device 0 Capability Identification (D2:F1)<br />
(Mirrored_D0_E0) ............................................................................... 199<br />
8.1.19 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F1)<br />
(Mirrored_D0_52) ............................................................................... 199<br />
8.1.20 MDEVEN—Mirror of Device 0 Device Enable (D2:F1)<br />
(Mirrored_D0_54) ............................................................................... 199<br />
8.1.21 BSM—Base of Stolen Memory Register (D2:F1) ............................... 200<br />
8.1.22 PMCAPID—Power Management Capabilities ID (D2:F1) .................. 200<br />
8.1.23 PMCAP—Power Management Capabilities (D2:F1) .......................... 200<br />
8.1.24 PMCS—Power Management Control/Status (D2:F1) ........................ 201<br />
8.1.25 SWSMI—Software SMI (D2:F1) ......................................................... 201<br />
8.1.26 ASLS—ASL Storage (D2:F1) ............................................................. 202<br />
8.2 Device 2 – PCI I/O Registers ............................................................................. 203<br />
8.2.1 MMIO Index—MMIO Address Register .............................................. 203<br />
8.2.2 MMIO Data—MMIO Data Register ..................................................... 203<br />
9 System Address Map ...................................................................................................... 205<br />
9.1 Legacy Address Range ...................................................................................... 207<br />
9.1.1 DOS Range (0h – 9_FFFFh) .............................................................. 208<br />
9.1.2 Legacy Video Area (A_0000h–B_FFFFh) .......................................... 208<br />
9.1.3 Expansion Area (C_0000h–D_FFFFh) ............................................... 209<br />
9.1.4 Extended System BIOS Area (E_0000h–E_FFFFh) .......................... 210<br />
9.1.5 System BIOS Area (F_0000h–F_FFFFh) ........................................... 210<br />
9.1.6 Programmable Attribute Map (PAM) Memory Area Details ................ 210<br />
9.2 Main Memory Address Range (1 MB to TOLUD) .............................................. 211<br />
9.2.1 ISA Hole (15 MB–16 MB) ................................................................... 212<br />
9.2.2 TSEG .................................................................................................. 212<br />
9.2.3 Pre-allocated Memory ......................................................................... 212<br />
9.3 PCI Memory Address Range (TOLUD – 4 GB) ................................................. 213<br />
9.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ................. 214<br />
9.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ................................................ 214<br />
9.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................ 214<br />
9.3.4 High BIOS Area .................................................................................. 214<br />
9.3.5 PCI <strong>Express</strong>* Configuration Address Space ...................................... 214<br />
9.3.6 PCI <strong>Express</strong>* Graphics Attach (Intel ®<br />
82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L GMCH Only) ............................ 215<br />
9.3.7 AGP DRAM Graphics Aperture .......................................................... 215<br />
9.3.8 Graphics Memory Address Ranges (Intel ® 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z<br />
GMCH Only) ....................................................................................... 216<br />
9.4 System Management Mode (SMM) ................................................................... 216<br />
9.4.1 SMM Space Definition ........................................................................ 217<br />
9.4.2 SMM Space Restrictions .................................................................... 217<br />
9.4.3 SMM Space Combinations ................................................................. 218<br />
9.4.4 SMM Control Combinations ................................................................ 218<br />
8 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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