Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0)
PCI Device: 0
Address Offset: 93h
Default Value: 00h
Access: R/W
Size: 8 bits
Host Bridge/DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h–
0D7FFFh.
Bit Access &
Default
7:6 Reserved
5:4 R/W
00 b
3:2 Reserved
1:0 R/W
00 b
Description
0D4000h–0D7FFFh Attribute (HIENABLE): This field controls the steering of read
and write cycles that address the BIOS area from 0D4000h to 0D7FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
0D0000h–0D3FFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to the DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to the
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 79