Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host Bridge/DRAM Controller Registers (D0:F0) 4.1.16 GGC—GMCH Graphics Control Register (D0:F0) (Intel ® 82945G/82945GC/82945GZ GMCH Only) PCI Device: 0 Address Offset: 52h Default Value: 0030h Access: R/W/L Size: 16 bits Bit Access & Default 15:7 Reserved 6:4 R/W/L 011 b Descriptions Graphics Mode Select (GMS): This field selects the amount of main memory that is pre-allocated to support the internal graphics device in VGA (non-linear) and native (linear) modes. BIOS ensures that memory is pre-allocated only when internal graphics is enabled. 000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), and the Sub-Class Code field within D2:F0 Class Code register is 80h. 001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame buffer. 010 = Reserved. 011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame buffer. 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved 3:2 Reserved 1 R/W 0 b 0 Reserved NOTE: This register is locked and becomes read only when the D_LCK bit in the SMRAM register is set. IGD VGA Disable (IVD): 0 = Enable. Device 2 (IGD) claims VGA cycles (memory and I/O); the Sub-Class Code within Device 2 Class Code register is 00. 1 = Disable. Device 2 (IGD) does not claim VGA cycles (memory and I/O); the Sub-Class Code field within D2:F0 Class Code register is 80h. 74 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0) 4.1.17 DEVEN—Device Enable (D0:F0) PCI Device: 0 Address Offset: 54h Default Value: 82945G/82945GC/82945GZ GMCH: 0000001Bh 82945P/82945PL MCH: 00000003h Access: R/W Size: 32 bits This register allows for enabling/disabling of PCI devices and functions that are within the (G)MCH. Bit Access & Default 31:5 Reserved 4 R/W 1b (GMCH) 0b (MCH) 3 R/W 1b (GMCH) 0b (MCH) 82945G/82945GC/82945GZ GMCH Description Internal Graphics Engine Function 1 (D2F1EN): 0 = Disable. Bus0:D2:F1 is disabled and hidden 1 = Enable. Bus0:D2:F1 is enabled and visible NOTE: Setting this bit to enabled when bit 3 is 0 has no meaning. 82945P/82945PL MCH Reserved. 82945G/82945GC/82945GZ GMCH Internal Graphics Engine Function 0 (D2F0EN): 0 = Disable. Bus0:D2:F0 is disabled and hidden 1 = Enable. Bus0:D2:F0 is enabled and visible 82945P/82945PL MCH Reserved 2 Reserved 1 R/W 1b 0 RO 1b 82945G/82945GC/82945P/82945PL (G)MCH PCI Express* Port (D1EN): 0 = Disable. Bus0:D1:F0 is disabled and hidden. 1 = Enable. Bus0:D1:F0 is enabled and visible. 82945GZ GMCH Reserved Host Bridge: Hardwired to 1. Bus0:D0:F0 can not be disabled. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 75
- Page 23 and 24: Term Description TOLM Top Of Low Me
- Page 25 and 26: Introduction � Supports four bank
- Page 27 and 28: Introduction 1.4 Graphics (Intel ®
- Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
- Page 31 and 32: 2 Signal Description Signal Descrip
- Page 33 and 34: 2.1 Host Interface Signals Signal D
- Page 35 and 36: Signal Name Type Description HREQ[4
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39 and 40: Signal Description 2.6 Analog Displ
- Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
- Page 59 and 60: Bit Access & Default 10:8 R/W 000b
- Page 61 and 62: Host Bridge/DRAM Controller Registe
- Page 63 and 64: 4.1 Device 0 Configuration Register
- Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
- Page 71 and 72: Host Bridge/DRAM Controller Registe
- Page 73: Host Bridge/DRAM Controller Registe
- Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
- Page 79 and 80: 4.1.21 PAM3—Programmable Attribut
- Page 81 and 82: 4.1.23 PAM5—Programmable Attribut
- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
- Page 85 and 86: Host Bridge/DRAM Controller Registe
- Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
- Page 89 and 90: 4.1.31 SKPD—Scratchpad Data (D0:F
- Page 91 and 92: Host Bridge/DRAM Controller Registe
- Page 93 and 94: Host Bridge/DRAM Controller Registe
- Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
- Page 97 and 98: 4.2.9 C0DRT1—Channel A DRAM Timin
- Page 99 and 100: Bit Access & Default 6:4 R/W 000b 3
- Page 101 and 102: Host Bridge/DRAM Controller Registe
- Page 103 and 104: 4.2.24 PMSTS—Power Management Sta
- Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
- Page 109 and 110: Host-PCI Express* Bridge Registers
- Page 111 and 112: Address Offset Host-PCI Express* Br
- Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
- Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
- Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
- Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
- Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
- Page 123 and 124: Host-PCI Express* Bridge Registers
Host Bridge/DRAM Controller Registers (D0:F0)<br />
4.1.17 DEVEN—Device Enable (D0:F0)<br />
PCI Device: 0<br />
Address Offset: 54h<br />
Default Value: 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH: 0000001Bh<br />
82<strong>945P</strong>/82<strong>945P</strong>L MCH: 00000003h<br />
Access: R/W<br />
Size: 32 bits<br />
This register allows for enabling/disabling of PCI devices and functions that are within the<br />
(G)MCH.<br />
Bit Access &<br />
Default<br />
31:5 Reserved<br />
4 R/W<br />
1b<br />
(GMCH)<br />
0b<br />
(MCH)<br />
3 R/W<br />
1b<br />
(GMCH)<br />
0b<br />
(MCH)<br />
82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH<br />
Description<br />
Internal Graphics Engine Function 1 (D2F1EN):<br />
0 = Disable. Bus0:D2:F1 is disabled and hidden<br />
1 = Enable. Bus0:D2:F1 is enabled and visible<br />
NOTE: Setting this bit to enabled when bit 3 is 0 has no meaning.<br />
82<strong>945P</strong>/82<strong>945P</strong>L MCH<br />
Reserved.<br />
82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH<br />
Internal Graphics Engine Function 0 (D2F0EN):<br />
0 = Disable. Bus0:D2:F0 is disabled and hidden<br />
1 = Enable. Bus0:D2:F0 is enabled and visible<br />
82<strong>945P</strong>/82<strong>945P</strong>L MCH<br />
Reserved<br />
2 Reserved<br />
1 R/W<br />
1b<br />
0 RO<br />
1b<br />
82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L (G)MCH<br />
PCI <strong>Express</strong>* Port (D1EN):<br />
0 = Disable. Bus0:D1:F0 is disabled and hidden.<br />
1 = Enable. Bus0:D1:F0 is enabled and visible.<br />
82<strong>945G</strong>Z GMCH<br />
Reserved<br />
Host Bridge: Hardwired to 1. Bus0:D0:F0 can not be disabled.<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 75
Change language