Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
Bit Access &
Default
27 R/W
0b
26 R/W
0b
25:3 Reserved
2:1 R/W
00b
0 R/W
0h
Description
128 MB Base Address Mask (128ADMSK): This bit is either part of the PCI
Express Base Address (R/W) or part of the Address Mask (RO, read 0b),
depending on the value of bits 2:1 in this register.
64 MB Base Address Mask (64ADMSK): This bit is either part of the PCI Express
Base Address (R/W) or part of the Address Mask (RO, read 0b), depending on the
value of bits 2:1 in this register
Length (LENGTH): This field describes the length of this region.
00 = 256 MB (buses 0–255). Bits 31:28 are decoded in the PCI Express Base
Address Field
01 = 128 MB (Buses 0–127). Bits 31:27 are decoded in the PCI Express Base
Address Field.
10 = 64 MB (Buses 0–63). Bits 31:26 are decoded in the PCI Express Base
Address Field.
11 = Reserved
PCIEXBAR Enable (PCIEXBAREN):
0 = The PCIEXBAR register is disabled. Memory read and write transactions
proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:26 are
R/W with no functionality behind them.
1 = The PCIEXBAR register is enabled. Memory read and write transactions
whose address bits 31:26 match PCIEXBAR will be translated to
configuration reads and writes within the (G)MCH.
72 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet