Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.14 PCIEXBAR—PCI Express* Register Range Base Address
(D0:F0) (Intel ® 82945G/82945GC/82945P/82945PL (G)MCH
Only)
PCI Device: 0
Address Offset: 48h
Default Value: E0000000h
Access: R/W
Size: 32 bits
This is the base address for the PCI Express configuration space. This window of addresses
contains the 4 KB of configuration space for each PCI Express device that can potentially be part
of the PCI Express hierarchy associated with the (G)MCH. This window of up to 256-MB does
not contain actual physical memory that can be addressed. The actual length is determined by a
field in this register. Each PCI Express hierarchy requires a PCI Express ase register. The
(G)MCH supports one PCI Express hierarchy.
The region reserved by this register does not alias to any PCI 2.3 compliant memory-mapped
space. For example, MCHBAR reserves a 16-KB space outside of PCIEXBAR space. It cannot be
overlaid on the space reserved by PCIEXBAR for device 0.
On reset, this register is disabled and must be enabled by writing a 1 to the enable field in this
register. This base address shall be assigned on a boundary consistent with the number of buses
defined by the Length field in this register), above TOLUD and still within total 32 bit
addressable memory space.
All other bits not decoded are read only 0. The PCI Express Base Address cannot be less than the
maximum address written to the top of physical memory register (TOLUD). Software must ensure
that these ranges do not overlap with known ranges located above TOLUD.
Bit Access &
Default
31:28 R/W
Eh
Description
PCI Express* Base Address: This field corresponds to bits 31:28 of the base
address for PCI Express enhanced configuration space. BIOS will program this
register resulting in a base address for a contiguous memory address space; size
is defined by bits 2:1 of this register.
This base address shall be assigned on a boundary consistent with the number of
buses (defined by the Length field in this register) above TOLUD and still within
total 32-bit addressable memory space. The address bits decoded depends on the
length of the region defined by this register.
The address used to access the PCI Express configuration space for a specific
device can be determined as follows:
PCI Express Base Address + Bus Number * 1 MB + Device Number * 32 KB +
Function Number * 4 KB
The address used to access the PCI Express configuration space for Device 1 in
this component would be PCI Express Base Address + 0 * 1 MB + 1 * 32 KB +
0 * 4 KB = PCI Express Base Address + 32 KB. Remember that this address is the
beginning of the 4 KB space that contains both the PCI compatible configuration
space and the PCI Express extended configuration space.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 71