Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base
Address (D0:F0)
PCI Device: 0
Address Offset: 44h
Default Value: 00000000h
Access: R/W
Size: 32 bits
This is the base address for the (G)MCH memory-mapped configuration space. There is no
physical memory within this 16-KB window that can be addressed. The 16 KB reserved by this
register does not alias to any PCI 2.3 compliant memory-mapped space.
On reset, the (G)MCH Memory Mapped Base Address field in this register is disabled and must
be enabled by writing a 1 to the MCHBAREN bit.
Bit Access &
Default
31:14 R/W
00000h
13:1 Reserved
0 R/W
0b
Description
(G)MCH Memory Mapped Base Address: This field corresponds to bits 31:14 of
the base address (G)MCH memory-mapped configuration space.
BIOS will program this register resulting in a base address for a 16-KB block of
contiguous memory address space. This register ensures that a naturally aligned
16-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH memory-mapped
register set.
MCHBAR Enable (MCHBAREN):
0 = MCHBAR is disabled and does not claim any memory.
1 = MCHBAR memory-mapped accesses are claimed and decoded appropriately
70 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet